DSPIC30F5015-30I/PT Microchip Technology Inc., DSPIC30F5015-30I/PT Datasheet - Page 154

• Manufacturer Part Number: DSPIC30F5015-30I/PT
• Description: DSP, 16-Bit, 66 KB Flash, 2KB RAM, 52 I/O, TQFP-64
• Manufacturer: Microchip Technology Inc.
• Type: DSPr

Specifications of DSPIC30F5015-30I/PT

• A/d Inputs: 16-Channels, 10-Bit
• Cpu Speed: 30 MIPS
• Eeprom Memory: 1K Bytes
• Input Output: 52
• Interface: CAN, I2C, SPI, UART/USART
• Ios: 52
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 64-pin TQFP
• Programmable Memory: 66K Bytes
• Ram Size: 2K Bytes
• Timers: 5-16-bit, 2-32-bit
• Voltage, Range: 2.5-5.5
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

dsPIC30F5015/5016
21.4
The conversion trigger will terminate acquisition and
start the requested conversions.
The SSRC<2:0> bits select the source of the
conversion trigger.
The SSRC bits provide for up to 5 alternate sources of
conversion trigger.
When SSRC<2:0> = 000, the conversion trigger is
under software control. Clearing the SAMP bit will
cause the conversion trigger.
When SSRC<2:0> = 111 (Auto-Start mode), the con-
version trigger is under A/D clock control. The SAMC
bits select the number of A/D clocks between the start
of acquisition and the start of conversion. This provides
the fastest conversion rates on multiple channels.
SAMC must always be at least 1 clock cycle.
Other trigger sources can come from timer modules,
Motor Control PWM module, or external interrupts.
21.5
Clearing the ADON bit during a conversion will abort
the current conversion and stop the sampling sequenc-
ing. The ADCBUF will not be updated with the partially
completed A/D conversion sample. That is, the
ADCBUF will continue to contain the value of the last
completed conversion (or the last value written to the
ADCBUF register).
If the clearing of the ADON bit coincides with an
auto-start, the clearing has a higher priority.
After the A/D conversion is aborted, a 2 T
required before the next sampling may be started by
setting the SAMP bit.
If sequential sampling is specified, the A/D will continue
at the next sample pulse which corresponds with the next
channel converted. If simultaneous sampling is specified,
the A/D will continue with the next multichannel group
conversion sequence.
DS70149C-page 152
Note:
Programming the Start of
Conversion Trigger
Aborting a Conversion
To operate the ADC at the maximum
specified conversion speed, the Auto-
Convert Trigger option should be selected
(SSRC = 111) and the Auto-Sample Time
bits
(SAMC = 00001). This configuration will
give a total conversion period (sample +
convert) of 13 T
The use of any other conversion trigger will
result
synchronize the external event to the ADC.
should
in
additional
AD
be
.
set
T
AD
to
cycles
AD
1
wait is
T
AD
to
21.6
The A/D conversion requires 12 T
A/D conversion clock is software selected using a 6-bit
counter. There are 64 possible options for T
EQUATION 21-1:
The internal RC oscillator is selected by setting the
ADRC bit.
For correct A/D conversions, the A/D conversion clock
(T
of 83.33 nsec (for V
“Electrical Characteristics” for minimum T
other operating conditions.
Example 21-1 shows a sample calculation for the
ADCS<5:0> bits, assuming a device operating speed
of 30 MIPS.
EXAMPLE 21-1:
21.7
The dsPIC30F 10-bit ADC specifications permit a
maximum
summarizes the conversion speeds for the dsPIC30F
10-bit ADC and the required operating conditions.
AD
) must be selected to ensure a minimum T
Therefore,
Set ADCS<5:0> = 5
Selecting the A/D Conversion
Clock
ADC Speeds
ADCS<5:0> = 2
T
Actual T
AD
1
= T
ADCS<5:0> = 2
Msps
CY
AD
T
T
* (0.5*(ADCS<5:0> +1))
AD
CY
DD
= 2 •
= 4.09
=
=
= 99 nsec
A/D CONVERSION CLOCK
A/D CONVERSION CLOCK
CALCULATION
= 33 nsec (30 MIPS)
= 84 nsec
© 2007 Microchip Technology Inc.
= 5V). Refer to Section 24.0
sampling
T
33 nsec
T
T
CY
2
AD
CY
84 nsec
2
33 nsec
(ADCS<5:0> + 1)
T
T
– 1
AD
CY
AD
(9 + 1)
. The source of the
rate.
– 1
– 1
AD
Table 21-1
AD
.
AD
under
time