MCP23S17-E/SP Microchip Technology Inc., MCP23S17-E/SP Datasheet - Page 18

• Manufacturer Part Number: MCP23S17-E/SP
• Description: I/O Port Expander, 16-Bit, SPI I'face, SDIP-28
• Manufacturer: Microchip Technology Inc.
• Type: Programmable Peripheral Interfacer

Specifications of MCP23S17-E/SP

• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

MCP23017/MCP23S17
REGISTER 1-6:
DS21952B-page 18
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W-0
BANK
BANK: Controls how the registers are addressed
1 = The registers associated with each port are separated into different banks
0 = The registers are in the same bank (addresses are sequential)
MIRROR: INT Pins Mirror bit
1 = The INT pins are internally connected
0 = The INT pins are not connected. INTA is associated with PortA and INTB is associated with PortB
SEQOP: Sequential Operation mode bit.
1 = Sequential operation disabled, address pointer does not increment.
0 = Sequential operation enabled, address pointer increments.
DISSLW: Slew Rate control bit for SDA output.
1 = Slew rate disabled.
0 = Slew rate enabled.
HAEN: Hardware Address Enable bit (MCP23S17 only).
Address pins are always enabled on MCP23017.
1 = Enables the MCP23S17 address pins.
0 = Disables the MCP23S17 address pins.
ODR: This bit configures the INT pin as an open-drain output.
1 = Open-drain output (overrides the INTPOL bit).
0 = Active driver output (INTPOL bit sets the polarity).
INTPOL: This bit sets the polarity of the INT output pin.
1 = Active-high.
0 = Active-low.
Unimplemented: Read as ‘0’.
MIRROR
R/W-0
IOCON – I/O EXPANDER CONFIGURATION REGISTER (ADDR 0x05)
W = Writable bit
‘1’ = Bit is set
SEQOP
R/W-0
DISSLW
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
HAEN
R/W-0
ODR
© 2007 Microchip Technology Inc.
x = Bit is unknown
INTPOL
R/W-0
U-0
—
bit 0