PIC18F4220-I/P Microchip Technology Inc., PIC18F4220-I/P Datasheet
PIC18F4220-I/P
Specifications of PIC18F4220-I/P
Available stocks
Related parts for PIC18F4220-I/P
PIC18F4220-I/P Summary of contents
Page 1
... PIC18F2220/2320/4220/4320 Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology 2003 Microchip Technology Inc. 28/40/44-Pin High-Performance, Data Sheet DS39599C ...
Page 2
... QS-9000 compliant for its PICmicro ® 8-bit MCUs ® code hopping EE OQ devices, Serial EEPROMs, microperipherals, non-volatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001 certified. 2003 Microchip Technology Inc. PowerInfo, Select Mode, ...
Page 3
... Program Memory Device Flash # Single Word (bytes) Instructions PIC18F2220 4096 2048 PIC18F2320 8192 4096 PIC18F4220 4096 2048 PIC18F4320 8192 4096 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 Peripheral Highlights: • High current sink/source 25 mA/25 mA • Three external interrupts • Capture/Compare/PWM (CCP) modules: - Capture is 16-bit, max ...
Page 4
... Note: Pin compatible with 40-pin PIC16C7X devices. DS39599C-page REF RB7/KBI3/PGD RB6/KBI2/PGC RB5/KBI1/PGM RB4/AN11/KBI0 RB3/AN9/CCP2* RB2/AN8/INT2 RB1/AN10/INT1 RB0/AN12/INT0 RD7/PSP7/P1D RD6/PSP6/P1C RD5/PSP5/P1B RD4/PSP4 RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/PSP2 RB7/KBI3/PGD RB6//KBI2/PGC RB5/KBI1/PGM RB4/AN11/KBI0 * RB3/AN9/CCP2 RB2/AN8/INT2 RB1/AN10/INT1 RB0/AN12/INT0 RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA 2003 Microchip Technology Inc. ...
Page 5
... V DD RB0/AN12/INT0 RB1/AN10/INT1 RB2/AN8/INT2 * RB3 is the alternate pin for the CCP2 pin multiplexing. 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 RC0/T1OSO/T1CKI OSC2/CLKO/RA6 3 OSC1/CLKI/RA7 30 4 PIC18F4220 PIC18F4320 RE2/AN7/ RE1/AN6/ RE0/AN5/ RA5/AN4/SS/LVDIN/C2OUT RA4/T0CKI/C1OUT 11 OSC2/CLKO/RA6 33 1 OSC1/CLKI/RA7 PIC18F4220 PIC18F4320 27 RE2/AN7/CS 7 RE1/AN6/ RE0/AN5/ RA5/AN4/SS/LVDIN/C2OUT RA4/T0CKI/C1OUT 11 DS39599C-page 3 ...
Page 6
... Appendix D: Migration from Baseline to Enhanced Devices.............................................................................................................. 370 Appendix E: Migration from Mid-Range to Enhanced Devices .......................................................................................................... 371 Appendix F: Migration from High-End to Enhanced Devices ............................................................................................................. 371 Index .................................................................................................................................................................................................. 373 On-Line Support................................................................................................................................................................................. 383 Systems Information and Upgrade Hot Line ...................................................................................................................................... 383 Reader Response .............................................................................................................................................................................. 384 PIC18F2220/2320/4220/4320 Product Identification System ............................................................................................................ 385 DS39599C-page 4 2003 Microchip Technology Inc. ...
Page 7
... When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com/cn to receive the most current information on all of our products. 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 DS39599C-page 5 ...
Page 8
... PIC18F2220/2320/4220/4320 NOTES: DS39599C-page 6 2003 Microchip Technology Inc. ...
Page 9
... DEVICE OVERVIEW This document contains device specific information for the following devices: • PIC18F2220 • PIC18F4220 • PIC18F2320 • PIC18F4320 This family offers the advantages of all PIC18 micro- controllers – namely, high computational performance at an economical price with the addition of high- endurance Enhanced Flash program memory ...
Page 10
... Stack Underflow (PWRT, OST), MCLR (optional), WDT WDT Yes Yes Yes Yes 75 Instructions 28-pin SPDIP 28-pin SPDIP 28-pin SOIC 28-pin SOIC Slave Port (present only on PIC18F4220 PIC18F4320 DC – 40 MHz DC – 40 MHz 4096 8192 2048 4096 512 512 256 256 20 20 Ports Ports ...
Page 11
... RE3 is available only when the MCLR Resets are disabled. 3: OSC1, OSC2, CLKI and CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. Refer to Section 2.0 “Oscillator Configurations” for additional information. 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 Data Bus<8> ...
Page 12
... PIC18F2220/2320/4220/4320 FIGURE 1-2: PIC18F4220/4320 BLOCK DIAGRAM Table Pointer <2> 21 inc/dec logic 21 21 PCLATU 20 Address Latch Program Memory PCU (8 Kbytes) Program Counter Data Latch 16 Table Latch 8 ROM Latch Instruction Register Instruction Decode & Control Internal (3) OSC1 Power-up Oscillator Block (3) OSC2 Oscillator Start-up Timer ...
Page 13
... ST = Schmitt Trigger input with CMOS levels O = Output OD = Open-drain (no diode to V Note 1: Default assignment for CCP2 when CCP2MX (CONFIG3H<0>) is set. 2: Alternate assignment for CCP2 when CCP2MX is cleared. 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 Buffer Type Type Master Clear (input) or programming voltage (input Master Clear (Reset) input ...
Page 14
... Digital I/O. I TTL Interrupt-on-change pin. I/O ST In-Circuit Debugger and ICSP programming clock pin. I/O TTL Digital I/O. I TTL Interrupt-on-change pin. I/O ST In-Circuit Debugger and ICSP programming data pin. CMOS = CMOS compatible input or output I = Input P = Power ) DD Description 2003 Microchip Technology Inc. ...
Page 15
... ST = Schmitt Trigger input with CMOS levels O = Output OD = Open-drain (no diode to V Note 1: Default assignment for CCP2 when CCP2MX (CONFIG3H<0>) is set. 2: Alternate assignment for CCP2 when CCP2MX is cleared. 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 Buffer Type Type PORTC is a bidirectional I/O port. I/O ST Digital I/O ...
Page 16
... PIC18F2220/2320/4220/4320 TABLE 1-3: PIC18F4220/4320 PINOUT I/O DESCRIPTIONS Pin Number Pin Name PDIP TQFP QFN MCLR/V /RE3 MCLR V PP RE3 OSC1/CLKI/RA7 13 30 OSC1 CLKI RA7 OSC2/CLKO/RA6 14 31 OSC2 CLKO RA6 RA0/AN0 2 19 RA0 AN0 RA1/AN1 3 20 RA1 AN1 RA2/AN2/V -/ REF REF RA2 ...
Page 17
... TABLE 1-3: PIC18F4220/4320 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PDIP TQFP QFN RB0/AN12/INT0 33 8 RB0 AN12 INT0 RB1/AN10/INT1 34 9 RB1 AN10 INT1 RB2/AN8/INT2 35 10 RB2 AN8 INT2 RB3/AN9/CCP2 36 11 RB3 AN9 (1) CCP2 RB4/AN11/KBI0 37 14 RB4 AN11 KBI0 RB5/KBI1/PGM 38 15 ...
Page 18
... PIC18F2220/2320/4220/4320 TABLE 1-3: PIC18F4220/4320 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PDIP TQFP QFN RC0/T1OSO/T1CKI 15 32 RC0 T1OSO T1CKI RC1/T1OSI/CCP2 16 35 RC1 T1OSI (2) CCP2 RC2/CCP1/P1A 17 36 RC2 CCP1 P1A RC3/SCK/SCL 18 37 RC3 SCK SCL RC4/SDI/SDA 23 42 RC4 SDI SDA RC5/SDO ...
Page 19
... TABLE 1-3: PIC18F4220/4320 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PDIP TQFP QFN RD0/PSP0 19 38 RD0 PSP0 RD1/PSP1 20 39 RD1 PSP1 RD2/PSP2 21 40 RD2 PSP2 RD3/PSP3 22 41 RD3 PSP3 RD4/PSP4 27 2 RD4 PSP4 RD5/PSP5/P1B 28 3 RD5 PSP5 P1B RD6/PSP6/P1C 29 4 RD6 ...
Page 20
... PIC18F2220/2320/4220/4320 TABLE 1-3: PIC18F4220/4320 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PDIP TQFP QFN RE0/AN5/ RE0 AN5 RD RE1/AN6/ RE1 AN6 WR RE2/AN7/ RE2 AN7 CS RE3 — — Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output ...
Page 21
... OSC2 pins to establish oscillation. Figure 2-1 shows the pin connections. The oscillator design requires the use of a parallel cut crystal. Note: Use of a series cut crystal may give a fre- quency out of the crystal manufacturers specifications. 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 FIGURE 2-1: ( OSC ...
Page 22
... Configuration Register 1H when DD OSC2 HS Mode Crystal OSC1 Osc of external EXTERNAL CLOCK INPUT OPERATION (HS OSC CONFIGURATION) OSC1 PIC18FXXXX (HS Mode) Open OSC2 PLL BLOCK DIAGRAM HS Osc Enable PLL Enable Phase F IN Comparator F OUT Loop Filter 4 VCO SYSCLK 2003 Microchip Technology Inc. ...
Page 23
... CONFIGURATION) OSC1/CLKI Clock from Ext. System PIC18FXXXX RA6 I/O (OSC2) 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 2.5 RC Oscillator For timing insensitive applications, the “RC” and “RCIO” device options offer additional cost savings. The RC oscillator frequency is a function of the supply voltage, the resistor (R ues and the operating temperature ...
Page 24
... There is no indication that the shift has occurred. Oper- ation of features that depend on the INTRC clock source frequency, such as the WDT, Fail-Safe Clock Monitor and peripherals, will also be affected by the change in frequency. /4, OSC 8 clock cycles (approximately 2003 Microchip Technology Inc. ...
Page 25
... Center frequency. Oscillator module is running at the calibrated frequency. 111111 • • 100000 = Minimum frequency (-12.5%, approximately) Legend Readable bit -n = Value at POR 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 U-0 R/W-0 R/W-0 R/W-0 — TUN5 TUN4 TUN3 • • ...
Page 26
... If the Timer1 oscillator is not enabled, then any attempt to set the SCS0 bit will be ignored recommended that the Timer1 oscillator be operating and stable before executing the SLEEP instruction or a very long delay may occur while the Timer1 oscillator starts. 2003 Microchip Technology Inc. ...
Page 27
... Sleep OSC1 Secondary Oscillator T1OSO T1OSCEN Enable Oscillator T1OSI OSCCON<6:4> Internal Oscillator Block INTRC Source 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 PIC18F2X20/4X20 CONFIG1H <3:0> HSPLL 4 x PLL LP, XT, HS, RC, EC Clock Source Option for Other Modules OSCCON<6:4> 8 MHz 111 4 MHz 110 2 MHz ...
Page 28
... Legend Readable bit - n = Value at POR DS39599C-page 26 (1) R/W-0 R/W-0 R R-0 IRCF1 IRCF0 OSTS IOFS (1) ( Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R/W-0 R/W-0 SCS1 SCS0 bit Bit is unknown 2003 Microchip Technology Inc. ...
Page 29
... EC LP, XT, and HS Note: See Table 4-1 in Section 4.0 “Reset” for time-outs due to Sleep and MCLR Reset. 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 If the Sleep mode is selected, all clock sources are stopped. Since all the transistor switching currents have been stopped, Sleep mode achieves the lowest current consumption of the device (only leakage currents) ...
Page 30
... PIC18F2220/2320/4220/4320 NOTES: DS39599C-page 28 2003 Microchip Technology Inc. ...
Page 31
... RC_IDLE 1 1x Note 1: Includes INTOSC and INTOSC postscaler, as well as the INTRC source. 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 For PIC18F2X20/4X20 devices, the power managed modes are invoked by using the existing SLEEP instruction. All modes exit to PRI_RUN mode when trig- gered by an interrupt, a Reset WDT time-out (PRI_RUN mode is the normal full power execution mode ...
Page 32
... SCS bits are unchanged during and after the wake-up. Figure 3-2 shows how the system is clocked during the clock source switch. The example assumes the device was in SEC_IDLE or SEC_RUN mode when a wake is triggered (the primary clock was configured in HSPLL mode). 2003 Microchip Technology Inc ...
Page 33
... Clearing IDLEN allows the CPU to be clocked. Setting IDLEN disables clocks to the CPU, effectively stopping program execution (see Register 2-2). The peripherals continue to be clocked regardless of the setting of the IDLEN bit. 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 WDT time-out Peripherals are causes a ... ...
Page 34
... TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL) OSC1 (1) T OST PLL Clock Output CPU Clock Peripheral Clock Program PC Counter Wake-up Event Note 1024 (approx). These intervals are not shown to scale. OST OSC PLL DS39599C-page PLL ( OSTS bit Set 2003 Microchip Technology Inc. ...
Page 35
... Peripheral Clock Program PC Counter Wake-up Event 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 When a wake-up event occurs, the CPU is clocked from the primary clock source. A delay of approxi- mately required between the wake-up event and when code execution starts. This is required to allow the CPU to become ready to execute instructions. ...
Page 36
... T1RUN bit is cleared, the OSTS bit is set and the primary clock is providing the system clock. The IDLEN and SCS bits are not affected by the wake-up; the Timer1 oscillator continues to run Clock Transition PLL ( Clock Transition OSTS bit Set 2003 Microchip Technology Inc. ...
Page 37
... These intervals are not shown to scale. OST OSC PLL 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 was executed and the INTOSC source was already stable, the IOFS bit will remain set. If the IRCF bits are all clear, the INTOSC output is not enabled and the IOFS bit will remain clear ...
Page 38
... Figure 3-6). When the clock switch is complete, the Timer1 oscillator is disabled, the T1RUN bit is cleared, the OSTS bit is set and the pri- mary clock is providing the system clock. The IDLEN and SCS bits are not affected by the wake-up Clock Transition 2003 Microchip Technology Inc. ...
Page 39
... INTRC OSC1 CPU Clock Peripheral Clock Program PC Counter 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 Note: Caution should be used when modifying a single IRCF bit possible to select a higher clock speed than is supported by the low V Improper device operation may result if the V If the IRCF bits are all clear, the INTOSC output is not enabled and the IOFS bit will remain clear ...
Page 40
... On all exits from Lower Power mode by interrupt, code execution branches to the interrupt vector if the GIE/GIEH bit (INTCON<7>) is set. Otherwise, code execution continues or resumes without branching (see Section 9.0 “Interrupts”). 2003 Microchip Technology Inc. ...
Page 41
... Execution continues during the INTOSC stabilization period. 5: Required delay when waking from Sleep and all Idle modes. This delay runs concurrently with any other required delays (see Section 3.3 “Idle Modes”). 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 Power Activity During Wake-up from ...
Page 42
... INTRC clock source is selected. Being able to adjust the INTOSC requires knowing when an adjustment is required, in which direction it should be made and in some cases, how large a change is needed. Three examples are shown but other techniques may be used. 2003 Microchip Technology Inc. ...
Page 43
... If the internally clocked timer value is greater than expected, then the internal oscillator block is running too fast – decrement OSCTUNE. 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 3.6.3 EXAMPLE – CCP IN CAPTURE MODE ...
Page 44
... PIC18F2220/2320/4220/4320 NOTES: DS39599C-page 42 2003 Microchip Technology Inc. ...
Page 45
... INTRC Note 1: This is the INTRC source from the internal oscillator block and is separate from the RC oscillator of the CLKI pin. 2: See Table 4-1 for time-out situations. 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 Most registers are not affected by a WDT wake-up since this is viewed as the resumption of normal oper- ation ...
Page 46
... D005) for BOR (parameter #35), the brown-out situ- DD for less than T . The chip will BOR rises above BOR ; it then will keep the chip in BOR (parameter PWRT while the Power-up BOR , the Power-up Timer will execute BOR 2003 Microchip Technology Inc. ...
Page 47
... Legend unchanged unknown unimplemented bit, read as ‘0’ Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the interrupt vector (0x000008h or 0x000018h). 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 (2) Power-up and Brown-out ...
Page 48
... --uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu (1) uuuu uuuu (1) uuuu -u-u (1) uu-u u-uu N/A N/A N/A N/A N/A ---- uuuu uuuu uuuu uuuu uuuu N/A N/A N/A N/A N/A 2003 Microchip Technology Inc. ...
Page 49
... See Table 4-2 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 MCLR Resets Power-on Reset, ...
Page 50
... Microchip Technology Inc. ...
Page 51
... See Table 4-2 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 MCLR Resets Power-on Reset, ...
Page 52
... PWRT Time-out OST Time-out Internal Reset FIGURE 4-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR Internal POR PWRT Time-out OST Time-out Internal Reset DS39599C-page 50 T PWRT T OST T PWRT T OST T PWRT T OST 2003 Microchip Technology Inc RISE < PWRT ): CASE CASE 2 DD ...
Page 53
... TIME-OUT SEQUENCE ON POR W/ PLL ENABLED (MCLR TIED MCLR Internal POR PWRT Time-out OST Time-out PLL Time-out Internal Reset Note 1024 clock cycles. OST max. First three stages of the PWRT timer. PLL 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 , V RISE > PWRT T OST T PWRT T ...
Page 54
... PIC18F2220/2320/4220/4320 NOTES: DS39599C-page 52 2003 Microchip Technology Inc. ...
Page 55
... Accessing a location between the physically implemented memory and the 2-Mbyte address will cause a read of all ‘0’s (a NOP instruction). The PIC18F2220 and PIC18F4220 each have 4 Kbytes of Flash memory and can store up to 2,048 single-word instructions. The PIC18F2320 and PIC18F4320 each have 8 Kbytes of Flash memory and can store up to 4,096 single-word instructions ...
Page 56
... This is not the same as a Reset, as the contents of the SFRs are not affected. Return Address Stack 11111 11110 11101 STKPTR<4:0> TOSL 34h 00011 001A34h Top-of-Stack 00010 000D58h 00001 00000 00010 2003 Microchip Technology Inc. ...
Page 57
... POP instruction. The POP instruc- tion discards the current TOS by decrementing the stack pointer. The previous value pushed onto the stack then becomes the TOS value. 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 U-0 R/W-0 R/W-0 — ...
Page 58
... LSB of PCL is fixed to a value of ‘0’. The PC increments address sequential instructions in the program memory. The CALL, GOTO and program branch RCALL, instructions write to the program counter directly. For these instructions, the contents of PCLATH and PCLATU are not transferred to the program counter. 2003 Microchip Technology Inc. ...
Page 59
... Instruction @ address SUB_1 All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed. 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 5.6 Instruction Flow/Pipelining An “ ...
Page 60
... Execute this word as a NOP REG3 ; continue code REG1 ; is RAM location 0? REG1, REG2 ; Yes, execute this word ; 2nd word of instruction REG3 ; continue code Word Address 000000h 000002h 000004h 000006h 000008h 00000Ah 00000Ch 00000Eh 000010h 000012h 000014h 2003 Microchip Technology Inc. ...
Page 61
... Data is transferred to/from program memory, one byte at a time. The Table Read/Table Write operation is discussed further in Section 6.1 “Table Reads and Table Writes”. 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 5.9 Data Memory Organization The data memory is implemented as static RAM. Each register in the data memory has a 12-bit address, allowing up to 4096 bytes of data memory ...
Page 62
... The BSR is ignored and the Access Bank is used. The first 128 bytes are general purpose RAM (from Bank 0). The second 128 bytes are Special Function Registers (from Bank 15). When The BSR specifies the bank used by the instruction. 2003 Microchip Technology Inc. ...
Page 63
... Legend: — = Unimplemented registers, read as ‘0’. Note 1: This register is not available on PIC18F2X20 devices. 2: This is not a physical register. 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 “core” are described in this section, while those related to the operation of the peripheral features are described in the section of that peripheral feature. ...
Page 64
... DC C 47, 68 ---x xxxx 47, 119 0000 0000 47, 119 xxxx xxxx T0PS1 T0PS0 47, 117 1111 1111 2003 Microchip Technology Inc. ...
Page 65
... These registers and/or bits are not implemented on the PIC18F2X20 devices and read as ‘0’. 6: The RE3 port bit is only available when MCLRE fuse (CONFIG3H<7>) is programmed to ‘0’. Otherwise, RE3 reads ‘0’. This bit is read-only. 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 Bit 4 Bit 3 ...
Page 66
... Microchip Technology Inc. ...
Page 67
... Note 1: For register file map detail, see Table 5-1. 2: The access bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the registers of the Access Bank. 3: The MOVFF instruction embeds the entire 12-bit address in the instruction. 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 5.11 Bank Select Register (BSR) The need for a large general purpose memory space dictates a RAM banking scheme ...
Page 68
... NOP (status bits are not affected indirect addressing write is performed when the target address is an FSRnH or FSRnL register, the data is written to the FSR register but no pre post-increment/decrement is performed. will be incremented 2003 Microchip Technology Inc. ...
Page 69
... INDIRECT ADDRESSING OPERATION Instruction Executed Opcode BSR<3:0> Instruction Fetched Opcode FIGURE 5-9: INDIRECT ADDRESSING 3 11 Note 1: For register file map detail, see Table 5-1. 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 0h RAM Address FFFh 12 File Address = access of an indirect addressing register File ...
Page 70
... The C and DC bits operate as a borrow and digit borrow bit respectively, in subtraction. U-0 U-0 R/W-x R/W-x — — Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R/W-x R/W-x R/W bit Bit is unknown 2003 Microchip Technology Inc. ...
Page 71
... A Brown-out Reset has not occurred (set by firmware only Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) Legend Readable bit - n = Value at POR 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 Note 1: If the BOREN configuration bit is set (Brown-out Reset enabled), the BOR bit is ‘1’ Power-on Reset. After a Brown- ...
Page 72
... PIC18F2220/2320/4220/4320 NOTES: DS39599C-page 70 2003 Microchip Technology Inc. ...
Page 73
... TBLPTRL Program Memory (TBLPTR) Note 1: Table Pointer points to a byte in program memory. 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 The program memory space is 16 bits wide while the data RAM space is 8 bits wide. Table reads and table writes move data between these two memory spaces DD through an 8-bit register (TABLAT) ...
Page 74
... Program memory is read using table read instructions. See Section 6.3 “Reading the Flash Program Memory” regarding table reads. Note: Interrupt flag bit, EEIF in the PIR2 register, is set when the write is complete. It must be cleared in software. 2003 Microchip Technology Inc. TABLAT ...
Page 75
... Initiates a memory read (Read takes one cycle cleared in hardware. The RD bit can only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1 Read completed Legend Readable bit - n = Value at POR ‘1’ = Bit is set 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 U-0 R/W-0 R/W-x — ...
Page 76
... The Least Significant bits (TBLPTR<5:0>) are ignored. Figure 6-3 describes the relevant boundaries of TBLPTR based on Flash program memory operations. Operation on Table Pointer 8 7 TBLPTRH LONG WRITE – TBLPTR<21:3> READ or WRITE – TBLPTR<21:0> TBLPTRL 0 2003 Microchip Technology Inc. ...
Page 77
... TBLRD*+ MOVFW TABLAT MOVWF WORD_ODD 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 The internal program memory is typically organized by words. The Least Significant bit of the address selects between the high and low bytes of the word. Figure 6-4 shows the interface between the internal program memory and the TABLAT ...
Page 78
... Execute a NOP. 9. Re-enable interrupts. ; load TBLPTR with the base ; address of the memory block ; point to Flash program memory ; enable write to memory ; enable Row Erase operation ; disable interrupts ; write 55H ; write AAH ; start erase (CPU stall) ; re-enable interrupts 2003 Microchip Technology Inc. ...
Page 79
... CFGS bit to access program memory; • set WREN bit to enable byte writes. 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 Since the Table Latch (TABLAT) is only a single byte, the TBLWT instruction has to be executed 8 times for each programming operation. All of the table write operations will essentially be short writes because only the holding registers are written ...
Page 80
... FSR0 ; present data to table latch ; short write ; to internal TBLWT holding register, increment TBLPTR ; loop until buffers are full 2003 Microchip Technology Inc. ...
Page 81
... PIE2 OSCFIE CMIE — Legend unknown unchanged reserved unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access. 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 ; disable interrupts ; required sequence ; write 55H ; write AAH ; start program (CPU stall) ; re-enable interrupts ...
Page 82
... PIC18F2220/2320/4220/4320 NOTES: DS39599C-page 80 2003 Microchip Technology Inc. ...
Page 83
... Control bit EEPGD determines if the access will be to program or data EEPROM memory. When clear, oper- ations will access the data EEPROM memory. When set, program memory is accessed. 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 Control bit CFGS determines if the access will be to the configuration registers or to program memory/data EEPROM memory ...
Page 84
... R = Readable bit - n = Value at POR DS39599C-page 82 U-0 R/W-0 R/W-x — FREE WRERR S = Settable only U = Unimplemented bit, read as ‘0’ Writable bit ‘1’ = Bit is set ‘0’ = Bit is cleared R/W-0 R/S-0 R/S-0 WREN WR RD bit Bit is unknown 2003 Microchip Technology Inc. ...
Page 85
... BSF INTCON, GIE SLEEP BCF EECON1, WREN 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 After a write sequence has been initiated, EECON1, EEADR and EEDATA cannot be modified. The WR bit will be inhibited from being set unless the WREN bit is set. The WREN bit must be set on a previous instruc- tion ...
Page 86
... POR, BOR Resets RBIF 0000 000x 0000 000u 0000 0000 0000 0000 0000 0000 0000 0000 — — RD xx-0 x000 uu-0 u000 CCP2IP 11-1 1111 ---1 1111 CCP2IF 00-0 0000 ---0 0000 CCP2IE 00-0 0000 ---0 0000 2003 Microchip Technology Inc. ...
Page 87
... Example 8-2 shows the sequence signed multiply. To account for the sign bits of the arguments, each argument’s Most Significant bit (MSb) is tested and the appropriate subtractions are done. 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 Making the multiplier execute in a single-cycle gives the following advantages: • ...
Page 88
... MOVF ARG2H, W SUBWFB RES3 ; CONT_CODE : SIGNED MULTIPLICATION ALGORITHM SIGNED MULTIPLY ROUTINE ; ARG1L * ARG2L -> ; PRODH:PRODL ; ; ; ARG1H * ARG2H -> ; PRODH:PRODL ; ; ; ARG1L * ARG2H -> ; PRODH:PRODL ; ; Add cross ; products ; ; ; ; ; ARG1H * ARG2L -> ; PRODH:PRODL ; ; Add cross ; products ; ; ; ; ARG2H:ARG2L neg? ; no, check ARG1 ; ; ; ; ARG1H:ARG1L neg? ; no, done ; ; ; 2003 Microchip Technology Inc. ...
Page 89
... Individual inter- rupts can be disabled through their corresponding enable bits. 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are ...
Page 90
... INT2IE INT2IP IPE IPEN GIEL/PEIE IPEN TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP INT0IF INT0IE INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP 2003 Microchip Technology Inc. Wake- Power Managed Mode Interrupt to CPU Vector to Location 0008h GIEH/GIE Interrupt to CPU Vector to Location 0018h GIEL\PEIE ...
Page 91
... A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared. Legend Readable bit - n = Value at POR 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 Note: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit ...
Page 92
... This feature allows for software polling. DS39599C-page 90 R/W-1 R/W-1 U-0 R/W-1 INTEDG1 INTEDG2 — TMR0IP W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared U-0 R/W-1 — RBIP bit Bit is unknown 2003 Microchip Technology Inc. ...
Page 93
... Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 U-0 R/W-0 R/W-0 — ...
Page 94
... R-0 R-0 R/W-0 R/W-0 RCIF TXIF SSPIF CCP1IF W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared 2003 Microchip Technology Inc. R/W-0 R/W-0 TMR2IF TMR1IF bit Bit is unknown ...
Page 95
... No TMR1 register capture occurred Compare mode TMR1 register compare match occurred (must be cleared in software TMR1 register compare match occurred PWM mode: Unused in this mode. Legend Readable bit - n = Value at POR 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 U-0 R/W-0 R/W-0 — EEIF BCLIF W = Writable bit U = Unimplemented bit, read as ‘ ...
Page 96
... Legend Readable bit - n = Value at POR DS39599C-page 94 R/W-0 R/W-0 R/W-0 R/W-0 RCIE TXIE SSPIE CCP1IE W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R/W-0 R/W-0 TMR2IE TMR1IE bit Bit is unknown 2003 Microchip Technology Inc. ...
Page 97
... TMR3IE: TMR3 Overflow Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 CCP2IE: CCP2 Interrupt Enable bit 1 = Enabled 0 = Disabled Legend Readable bit - n = Value at POR 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 U-0 R/W-0 R/W-0 — EEIE BCLIE W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘ ...
Page 98
... Legend Readable bit - n = Value at POR DS39599C-page 96 R/W-1 R/W-1 R/W-1 R/W-1 RCIP TXIP SSPIP CCP1IP W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R/W-1 R/W-1 TMR2IP TMR1IP bit Bit is unknown 2003 Microchip Technology Inc. ...
Page 99
... TMR3IP: TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 CCP2IP: CCP2 Interrupt Priority bit 1 = High priority 0 = Low priority Legend Readable bit - n = Value at POR 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 U-0 R/W-1 R/W-1 — EEIP BCLIP W = Writable bit U = Unimplemented bit, read as ‘0’ ...
Page 100
... A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) Legend Readable bit - n = Value at POR DS39599C-page 98 U-0 U-0 R/W-1 R-1 — — Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R-1 R/W-0 R/W-0 PD POR BOR bit Bit is unknown 2003 Microchip Technology Inc. ...
Page 101
... USER ISR CODE ; MOVFF BSR_TEMP, BSR MOVF W_TEMP, W MOVFF STATUS_TEMP, STATUS 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 9.8 PORTB Interrupt-on-Change An input change on PORTB<7:4> sets flag bit, RBIF (INTCON<0>). The interrupt can be enabled/disabled by setting/clearing enable bit, RBIE (INTCON<3>). Interrupt priority for PORTB interrupt-on-change is determined by the value contained in the interrupt priority bit, RBIP (INTCON2< ...
Page 102
... PIC18F2220/2320/4220/4320 NOTES: DS39599C-page 100 2003 Microchip Technology Inc. ...
Page 103
... Port Note 1: I/O pins have diode protection to V 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 10.1 PORTA, TRISA and LATA Registers PORTA is an 8-bit wide, bidirectional port. The corre- sponding data direction register is TRISA. Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i ...
Page 104
... I/O pins have protection diodes to V and BLOCK DIAGRAM OF RA4/T0CKI PIN I/O pin N Data Latch Schmitt CK Q Trigger TRIS Latch Input Buffer and BLOCK DIAGRAM OF RA7 PIN To Oscillator (1) N I/O pin TTL Input Buffer and 2003 Microchip Technology Inc. ...
Page 105
... Shaded cells are not used by PORTA. Note 1: RA7:RA6 and their associated latch and data direction bits are enabled as I/O pins based on oscillator configuration; otherwise, they are read as ‘0’. 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 Buffer Function TTL Input/output or analog input ...
Page 106
... From other EN RB7:RB5 and RB4 pins RB7:RB5 in Serial Programming Mode Note 1: I/O pins have diode protection enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>). 2003 Microchip Technology Inc Weak P Pull-up (1) I/O pin ST Buffer Q1 RD PORTB ...
Page 107
... PORTB CK Data Latch D WR TRISB CK TRIS Latch RD TRISC RD PORTB CCP2 Input Analog Input Mode To A/D Converter Note 1: I/O pins have diode protection to V 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 FIGURE 10- (2) RBPU Weak P Pull-up Data Bus WR LATB (1) or PORTB I/O pin ...
Page 108
... POR, BOR Resets RB0 xxxq qqqq uuuu uuuu xxxx xxxx uuuu uuuu 1111 1111 1111 1111 RBIF 0000 000x 0000 000u RBIP 1111 -1-1 1111 -1-1 INT1IF 11-0 0-00 11-0 0-00 PCFG0 --00 0000 --00 0000 2003 Microchip Technology Inc. ...
Page 109
... I/O pins have diode protection Port/Peripheral Select signal selects between port data (output) and peripheral output. 3: Peripheral Output Enable is only active if Peripheral Select is active. 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 Note Power-on Reset, these pins are configured as digital inputs. The contents of the TRISC register are affected by peripheral overrides ...
Page 110
... Input/output port pin, Addressable USART Asynchronous Receive or Addressable USART Synchronous Data. Bit 4 Bit 3 Bit 2 Bit 1 RC4 RC3 RC2 RC1 mode). Value on Value on Bit 0 all other POR, BOR Resets RC0 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu 1111 1111 1111 1111 2003 Microchip Technology Inc. ...
Page 111
... RD TRISD RD PORTD PSP Write Note 1: I/O pins have diode protection to V 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 PORTD can also be configured as an 8-bit wide micro- processor port (Parallel Slave Port) by setting control bit, PSPMODE (TRISE<4>). In this mode, the input buffers are TTL. See Section 10.6 “Parallel Slave Port” ...
Page 112
... V SS TTL Buffer Schmitt Trigger Input Buffer Value on Value on Bit 0 all other POR, BOR Resets RD0 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu 1111 1111 1111 1111 0000 -111 0000 -111 0000 0000 0000 0000 2003 Microchip Technology Inc. ...
Page 113
... Value used to ; initialize data ; direction MOVWF TRISC ; Set RE<0> as inputs ; RE<1> as outputs ; RE<2> as inputs 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 10.5.1 PORTE IN 28-PIN DEVICES For PIC18F2X20 devices, PORTE is only available when Master (CONFIG3H<7> = 0). In these cases, PORTE is a single bit, input only port comprised of RE3 only. The pin operates as previously described ...
Page 114
... Value at POR DS39599C-page 112 R-0 R/W-0 R/W-0 U-0 IBOV PSPMODE — Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R/W-1 R/W-1 R/W-1 TRISE2 TRISE1 TRISE0 bit Bit is unknown 2003 Microchip Technology Inc. ...
Page 115
... Shaded cells are not used by PORTE. Note 1: Implemented only when Master Clear functionality is disabled (CONFIG3H<7> = 0). 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 Function (1) Input/output port pin, analog input or read control input in Parallel Slave Port mode ...
Page 116
... Set Interrupt Flag PSPIF (PIR1<7>) Note: I/O pins have diode protection to V PORTD AND PORTE BLOCK DIAGRAM (PARALLEL SLAVE PORT) One bit of PORTD D Q RDx pin CK TTL PORTE Pins Read RD TTL Chip Select CS TTL Write WR TTL and 2003 Microchip Technology Inc. ...
Page 117
... ADIF RCIF PIE1 PSPIE ADIE RCIE IPR1 PSPIP ADIP RCIP ADCON1 — — VCFG1 Legend unknown unchanged unimplemented, read as ‘0’. Shaded cells are not used by the Parallel Slave Port. 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 Bit 4 Bit 3 Bit 2 Bit 1 — ...
Page 118
... PIC18F2220/2320/4220/4320 NOTES: DS39599C-page 116 2003 Microchip Technology Inc. ...
Page 119
... Legend Readable bit - n = Value at POR 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 Figure 11-1 shows a simplified block diagram of the Timer0 module in 8-bit mode and Figure 11-2 shows a simplified block diagram of the Timer0 module in 16-bit mode. The T0CON register (Register 11- readable and writable register that controls all the aspects of Timer0, including the prescale selection ...
Page 120
... T0PS2, T0PS1, T0PS0 0 Sync with Internal TMR0L Clocks delay PSA Data Bus 8 TMR0 Set Interrupt Flag bit TMR0IF on Overflow Set Interrupt TMR0 Flag bit TMR0IF High Byte on Overflow 8 Read TMR0L Write TMR0L 8 8 TMR0H 8 Data Bus<7:0> 2003 Microchip Technology Inc. ...
Page 121
... PORTA Data Direction Register Legend unknown unchanged unimplemented locations read as ‘0’. Shaded cells are not used by Timer0. Note 1: RA6 and RA7 are enabled as I/O pins depending on the oscillator mode selected in Configuration Word 1H. 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 11.2.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control (i.e., it can be changed “ ...
Page 122
... PIC18F2220/2320/4220/4320 NOTES: DS39599C-page 120 2003 Microchip Technology Inc. ...
Page 123
... Enables Timer1 0 = Stops Timer1 Legend Readable bit - n = Value at POR 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 Register 12-1 details the Timer1 Control register. This register controls the operating mode of the Timer1 module and contains the Timer1 Oscillator Enable bit (T1OSCEN). Timer1 can be enabled or disabled by setting or clearing control bit, TMR1ON (T1CON< ...
Page 124
... T1CKPS1:T1CKPS0 TMR1CS 8 CCP Special Event Trigger CLR TMR1L TMR1ON on/off 1 T1OSCEN F /4 OSC Enable Internal 0 (1) Oscillator Clock TMR1CS T1CKPS1:T1CKPS0 Synchronized 0 Clock Input 1 Synchronize det 2 Peripheral Clocks Synchronized 0 Clock Input 1 T1SYNC Synchronize Prescaler det 2 Peripheral Clocks 2003 Microchip Technology Inc. ...
Page 125
... Capacitor values are for design guidance only. 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 12.3 Timer1 Oscillator Layout Considerations The Timer1 oscillator circuit draws very little power during operation. Due to the low power nature of the oscillator, it may also be sensitive to rapidly changing signals in close proximity ...
Page 126
... For this method to be accurate, Timer1 must operate in Asynchronous mode and the Timer1 overflow interrupt must be enabled (PIE1<0> shown in the rou- tine, RTCinit. The Timer1 oscillator must also be enabled and running at all times. 2003 Microchip Technology Inc. ...
Page 127
... Shaded cells are not used by the Timer1 module. Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X20 devices; always maintain these bits clear. 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 ; Preload TMR1 register pair ...
Page 128
... PIC18F2220/2320/4220/4320 NOTES: DS39599C-page 126 2003 Microchip Technology Inc. ...
Page 129
... Prescaler Prescaler Prescaler is 16 Legend Readable bit - n = Value at POR 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 13.1 Timer2 Operation Timer2 can be used as the PWM time base for the PWM mode of the CCP module. The TMR2 register is readable and writable and is cleared on any device Reset ...
Page 130
... POR, BOR Resets RBIF 0000 000x 0000 000u TMR1IF 0000 0000 0000 0000 TMR1IE 0000 0000 0000 0000 TMR1IP 1111 1111 1111 1111 0000 0000 0000 0000 1111 1111 1111 1111 SCS0 0000 qq00 0000 qq00 2003 Microchip Technology Inc. ...
Page 131
... TMR3ON: Timer3 On bit 1 = Enables Timer3 0 = Stops Timer3 Legend Readable bit - n = Value at POR 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 Figure 14 simplified block diagram of the Timer3 module. Register 14-1 shows the Timer3 Control register. This register controls the operating mode of the Timer3 module and sets the CCP clock source. ...
Page 132
... Oscillator Clock TMR3CS T3CKPS1:T3CKPS0 8 CCP Special Event Trigger T3CCPx TMR3 CLR TMR3L TMR3ON On/Off OSC Internal 0 (1) Clock T3CKPS1:T3CKPS0 TMR3CS Synchronized Clock Input Synchronize det 2 Peripheral Clocks Synchronized 0 Clock Input 1 T3SYNC Synchronize Prescaler det 2 Peripheral Clocks 2003 Microchip Technology Inc. ...
Page 133
... T1CKPS1 T1CKPS0 T1OSCEN T1SYNC T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 Legend unknown unchanged unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module. 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 14.4 Resetting Timer3 Using a CCP Trigger Output If the CCP module is configured in Compare mode ...
Page 134
... PIC18F2220/2320/4220/4320 NOTES: DS39599C-page 132 2003 Microchip Technology Inc. ...
Page 135
... Compare mode, trigger special event (CCP2IF bit is set) 11xx = PWM mode Legend Readable bit - n = Value at POR 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 Note: In 28-pin devices, both CCP1 and CCP2 function as standard CCP modules. In 40-pin devices, CCP1 is implemented as an Enhanced CCP module, offering addi- tional capabilities in PWM mode ...
Page 136
... CCPR2L (low byte) and CCPR2H (high byte). The CCP2CON register controls the operation of CCP2. All are readable and writable. CCP2 functions identically to CCP1 except for the enhanced PWM modes offered by CCP2 Interaction 2003 Microchip Technology Inc. ...
Page 137
... Prescaler CCP2 pin and Edge Detect CCP2CON<3:0> Q’s 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 15.3.3 SOFTWARE INTERRUPT When the Capture mode is changed, a false capture interrupt may be generated. The user should keep bit CCP1IE (PIE1<2>) clear to avoid false interrupts and should clear the flag bit, CCP1IF, following any such change in operating mode ...
Page 138
... Set Flag bit CCP1IF Output Logic Match CCP1CON<3:0> Mode Select TMR1H Special Event Trigger Set Flag bit CCP2IF T3CCP1 T3CCP2 Output Logic Match CCP2CON<3:0> Mode Select CCPR1H CCPR1L Comparator 1 0 T3CCP2 TMR1L TMR3H TMR3L 0 1 Comparator CCPR2H CCPR2L 2003 Microchip Technology Inc. ...
Page 139
... T3CCP2 T3CKPS1 T3CKPS0 Legend unknown unchanged unimplemented, read as ‘0’. Shaded cells are not used by Capture and Timer1. Note 1: These bits are reserved on the PIC18F2X20 devices; always maintain these bits clear. 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 Bit 4 Bit 3 Bit 2 Bit 1 ...
Page 140
... CCPR1H until a match between PR2 and TMR2 occurs (i.e., the period is complete). In PWM mode, CCPR1H is a read-only register. • OSC (TMR2 Prescale Value) T • (TMR2 Prescale Value) OSC 2003 Microchip Technology Inc. ...
Page 141
... Legend unknown unchanged unimplemented, read as ‘0’. Shaded cells are not used by PWM and Timer2. Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X20 devices; always maintain these bits clear. 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 15.5.3 SETUP FOR PWM OPERATION ...
Page 142
... PIC18F2220/2320/4220/4320 NOTES: DS39599C-page 140 2003 Microchip Technology Inc. ...
Page 143
... PWM mode, P1A, P1C active-low, P1B, P1D active-low Legend Readable bit - n = Value at POR 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 The ECCP module differs from the CCP with the addi- tion of an enhanced PWM mode which allows for output channels, user-selectable polarity, dead band control and automatic shutdown and restart ...
Page 144
... PWM Operation”. The latter is more generic but will work for either single or multi output PWM. CCP1CON RC2 RD5 CCP1 RD5/PSP5 00xx11xx P1A P1B 10xx11xx P1A P1B x1xx11xx RD6 RD7 RD6/PSP6 RD7/PSP7 RD6/PSP6 RD6/PSP6 P1C P1D 2003 Microchip Technology Inc. ...
Page 145
... D.C. PR2 Note: The 8-bit timer TMR2 register is concatenated with the 2-bit internal Q clock or 2 bits of the prescaler to create the 10-bit time base. 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 waveforms do not exactly match the standard PWM waveforms but are instead offset by one full instruction cycle ( ...
Page 146
... Delay = (PWM1CON<6:0>) OSC Note 1: Dead band delay is programmed using the PWM1CON register (see Section 16.4.4 “Programmable Dead Band Delay”). DS39599C-page 144 0 Duty Cycle Period (1) (1) Delay Delay 0 Duty Cycle Period (1) (1) Delay Delay 2003 Microchip Technology Inc. PR2+1 PR2+1 ...
Page 147
... TRISC<2> and TRISD<5> bits must be cleared to configure P1A and P1B as outputs. FIGURE 16-5: EXAMPLES OF HALF-BRIDGE OUTPUT MODE APPLICATIONS Standard Half-Bridge Circuit (“Push-Pull”) PIC18F4220/4320 Half-Bridge Output Driving a Full-Bridge Circuit PIC18F4220/4320 P1A P1B 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 FIGURE 16-4: Period ...
Page 148
... P1A, P1B, P1C and P1D outputs are multiplexed with the PORTC<2> and PORTD<5:7> data latches. The TRISC<2> and TRISD<5:7> bits must be cleared to make the P1A, P1B, P1C and P1D pins output. Period Duty Cycle Period Duty Cycle (1) (1) 2003 Microchip Technology Inc. ...
Page 149
... FIGURE 16-7: EXAMPLE OF FULL-BRIDGE APPLICATION PIC18F4220/4320 P1A P1B P1C P1D 16.4.3.1 Direction Change in Full-Bridge Mode In the Full-Bridge Output mode, the P1M1 bit in the CCP1CON register allows users to control the forward/ reverse direction. When the application firmware changes this direction control bit, the module will assume the new direction on the next PWM cycle ...
Page 150
... Note 1: All signals are shown as active-high the turn-on delay of power switch QC and its driver the turn-off delay of power switch QD and its driver. off DS39599C-page 148 (1) Period DC (Note 2) Forward Period Reverse Period Period (1) DC (3) t off (2, – t off on 2003 Microchip Technology Inc. ...
Page 151
... OSC transition active and the actual time it transitions active. Legend Readable bit - n = Value at POR 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 A shutdown event can be caused by either of the two comparator modules or the INT0 pin (or any combina- tion of these three sources). The comparators may be used to monitor a voltage input proportional to a current being monitored in the bridge circuit ...
Page 152
... Pins B and D tri-state Legend Readable bit - n = Value at POR DS39599C-page 150 R/W-0 R/W-0 R/W-0 R/W-0 PSSAC1 PSSAC0 W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R/W-0 R/W-0 PSSBD1 PSSBD0 bit Bit is unknown 2003 Microchip Technology Inc. ...
Page 153
... Activity Dead Time Duty Cycle Shutdown Event ECCPASE bit 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 16.4.6 START-UP CONSIDERATIONS When the ECCP module is used in the PWM mode, the application hardware must use the proper external pull- up and/or pull-down resistors on the PWM output pins. ...
Page 154
... EFFECTS OF A RESET Both Power-on and subsequent Resets will force all ports to Input mode and the CCP registers to their Reset states. This forces the Enhanced CCP module to reset to a state compatible with the standard CCP module. 2003 Microchip Technology Inc. is enabled ...
Page 155
... PWM1CON PRSEN PDC6 PDC5 OSCCON IDLEN IRCF2 IRCF1 Legend unknown unchanged unimplemented, read as ‘0’. Shaded cells are not used by the ECCP module in enhanced PWM mode. 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 Bit 4 Bit 3 Bit 2 Bit 1 INT0IE RBIE TMR0IF INT0IF RI TO ...
Page 156
... PIC18F2220/2320/4220/4320 NOTES: DS39599C-page 154 2003 Microchip Technology Inc. ...
Page 157
... MSSP 2 module is operated in SPI mode. Additional details are provided under the individual sections. 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 17.3 SPI Mode The SPI mode allows 8 bits of data to be synchronously transmitted and received, simultaneously. All four ...
Page 158
... During transmission, the SSPBUF is not double- buffered. A write to SSPBUF will write to both SSPBUF and SSPSR. R-0 R-0 R-0 CKE D Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R-0 R-0 R-0 R bit Bit is unknown 2003 Microchip Technology Inc. ...
Page 159
... SPI Master mode, clock = F 0000 = SPI Master mode, clock = F Note: Bit combinations not specifically listed here are either reserved or implemented mode only. Legend Readable bit - n = Value at POR 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 R/W-0 R/W-0 R/W-0 SSPEN CKP SSPM3 /64 OSC ...
Page 160
... Example 17-1 shows the loading of the SSPBUF (SSPSR) for data transmission. The SSPSR is not directly readable or writable and can only be accessed by addressing the SSPBUF register. Additionally, the MSSP Status register (SSPSTAT) indicates the various status conditions. 2003 Microchip Technology Inc. ...
Page 161
... Serial Input Buffer (SSPBUF) Shift Register (SSPSR) LSb MSb PROCESSOR 1 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 17.3.4 TYPICAL CONNECTION Register 17-2 shows a typical connection between two microcontrollers. The master controller (Processor 1) initiates the data transfer by sending the SCK signal. Data is shifted out of both shift registers on their pro- grammed clock edge and latched on the opposite edge of the clock ...
Page 162
... SMP bit. The time when the SSPBUF is loaded with the received data is shown. bit 2 bit 5 bit 4 bit 3 bit 1 bit 5 bit 4 bit 2 bit 1 bit Clock Modes bit 0 bit 0 bit 0 bit 0 Next Q4 Cycle after Q2 2003 Microchip Technology Inc. ...
Page 163
... SSPIF Interrupt Flag SSPSR to SSPBUF 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 is tri-stated, even if in the middle of a transmitted byte. External pull-up/pull-down resistors may be desirable, depending on the application. Note 1: When the SPI is in Slave mode with SS pin control enabled (SSPCON1<3:0> = 0100), the SPI module will reset when the SS pin is set high ...
Page 164
... SDI (SMP = 0) bit 7 Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF DS39599C-page 162 bit 6 bit 2 bit 5 bit 4 bit 3 bit 6 bit 5 bit 4 bit 2 bit 3 bit 1 bit 0 bit 0 Next Q4 Cycle after Q2 bit 1 bit 0 bit 0 Next Q4 Cycle after Q2 2003 Microchip Technology Inc. ...
Page 165
... Legend unknown unchanged unimplemented, read as ‘0’. Shaded cells are not used by the MSSP in SPI mode. Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X20 devices; always maintain these bits clear. 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 17.3.8.1 Slave in Power Managed Modes In Slave mode, the SPI Transmit/Receive Shift register operates asynchronously to the device ...
Page 166
... SSPIF interrupt is set. Addr Match During transmission, the SSPBUF is not double- buffered. A write to SSPBUF will write to both SSPBUF and SSPSR. Set, Reset S, P bits (SSPSTAT reg operation mode operation. The 2 C Slave mode. When 2003 Microchip Technology Inc. ...
Page 167
... Data transmit complete (does not include the ACK and Stop bits), SSPBUF is empty In Receive mode Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty Legend Readable bit - n = Value at POR 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 2 C MODE) R-0 R-0 R-0 D/A ...
Page 168
... R/W-0 R/W-0 R/W-0 SSPEN CKP SSPM3 SSPM2 /(4 * (SSPADD + 1)) OSC W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R/W-0 R/W-0 SSPM1 SSPM0 bit conditions were not valid for x = Bit is unknown 2003 Microchip Technology Inc. ...
Page 169
... For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I this bit may not be set (no spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled). Legend Readable bit - n = Value at POR 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 2 C MODE) R/W-0 R/W-0 R/W-0 ...
Page 170
... Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF. 7. Receive Repeated Start condition. 8. Receive first (high) byte of address (bits SSPIF and BF are set). 9. Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF. 2003 Microchip Technology Inc. ...
Page 171
... The clock must be released by setting bit, CKP (SSPCON1<4>). See Section 17.4.4 “Clock Stretching” for more detail. 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 17.4.3.3 Transmission When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPSTAT register is set ...
Page 172
... PIC18F2220/2320/4220/4320 2 FIGURE 17- SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS) DS39599C-page 170 2003 Microchip Technology Inc. ...
Page 173
... FIGURE 17- SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS) 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 DS39599C-page 171 ...
Page 174
... PIC18F2220/2320/4220/4320 2 FIGURE 17-10 SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS) DS39599C-page 172 2003 Microchip Technology Inc. ...
Page 175
... FIGURE 17-11 SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS) 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 DS39599C-page 173 ...
Page 176
... R/W bit set to ‘1’. After the third address sequence is performed, the UA bit is not set, the module is now configured in Transmit mode and clock stretching is controlled by the BF flag as in 7-bit Slave Transmit mode (see Figure 17-11). 2003 Microchip Technology Inc. ...
Page 177
... SDA DX SCL CKP WR SSPCON1 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 remain low until the CKP bit is set and all other 2 devices on the I C bus have deasserted SCL. This ensures that a write to the CKP bit will not violate the minimum high time requirement for SCL (see Figure 17-12) ...
Page 178
... PIC18F2220/2320/4220/4320 2 FIGURE 17-13 SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS) DS39599C-page 176 2003 Microchip Technology Inc. ...
Page 179
... FIGURE 17-14 SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 10-BIT ADDRESS) 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 DS39599C-page 177 ...
Page 180
... UA bit will not is enabled be set and the slave will begin receiving data after the Acknowledge (Figure 17-15). Address is compared to general call address after ACK, set interrupt R ACK Cleared in software SSPBUF is read Receiving Data ACK ‘0’ ‘1’ 2003 Microchip Technology Inc. ...
Page 181
... Generate a Stop condition on SDA and SCL. FIGURE 17-16: MSSP BLOCK DIAGRAM (I SDA SDA In SCL SCL In Bus Collision 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 Note: The MSSP module, when configured Master mode, does not allow queueing of events. For instance, the user is not ...
Page 182
... SSPCON2 register (SSPCON2<6>). 10. The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSPIF bit. 11. The user generates a Stop condition by setting the Stop Enable bit, PEN (SSPCON2<2>). 12. Interrupt is generated once the Stop condition is complete. 2003 Microchip Technology Inc. ...
Page 183
... Actual clock rate will depend on bus conditions. Bus capacitance can increase rise time and extend the low time of the clock period, reducing the effective clock frequency (see Section 17.4.7.2 “Clock Arbitration”). 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 17.4.7.1 Baud Rate Generation in Power ...
Page 184
... DX-1 SCL allowed to transition high BRG decrements on Q2 and Q4 cycles 02h 01h 00h (hold off) SCL is sampled high, reload takes place and BRG starts its count 03h 02h 2003 Microchip Technology Inc. ...
Page 185
... C module is reset into its Idle state. FIGURE 17-19: FIRST START BIT TIMING Write to SEN bit occurs here SDA SCL 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 17.4.8.1 WCOL Status Flag If the user writes the SSPBUF when a Start sequence is in progress, the WCOL is set and the contents of the buffer are unchanged (the write doesn’ ...
Page 186
... SSPCON2 is disabled until the Repeated Start condition is complete. Set S (SSPSTAT<3>) SDA = 1, At completion of Start bit, SCL = 1 hardware clears RSEN bit and sets SSPIF BRG BRG BRG Write to SSPBUF occurs here T BRG Sr = Repeated Start 1st bit T BRG 2003 Microchip Technology Inc. ...
Page 187
... SSPSR is still shifting out a data byte), the WCOL is set and the contents of the buffer are unchanged (the write doesn’t occur). WCOL must be cleared in software. 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 17.4.10.3 ACKSTAT Status Flag In Transmit mode, the ACKSTAT bit (SSPCON2<6>) is ...
Page 188
... PIC18F2220/2320/4220/4320 2 FIGURE 17-21 MASTER MODE WAVEFORM (TRANSMISSION 10-BIT ADDRESS) DS39599C-page 186 2003 Microchip Technology Inc. ...
Page 189
... FIGURE 17-22 MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS) 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 DS39599C-page 187 ...
Page 190
... SDA sampled high. P bit (SSPSTAT<4>) is set. PEN bit (SSPCON2<2>) is cleared by hardware and the SSPIF bit is set T BRG BRG BRG BRG SCL brought high after T BRG SDA asserted low before rising edge of clock to setup Stop condition Cleared in software BRG 2003 Microchip Technology Inc. ...
Page 191
... An Acknowledge Condition FIGURE 17-25: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE Data changes while SCL = 0 SDA SCL BCLIF 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 17.4.17 MULTI -MASTER COMMUNICATION, BUS COLLISION AND BUS ARBITRATION 2 C module Multi-Master mode support is achieved by bus arbitra- tion ...
Page 192
... Repeated Start or Stop conditions. SEN cleared automatically because of bus collision. SSP module reset into Idle state. SSPIF and BCLIF are cleared in software SSPIF and BCLIF are cleared in software 2003 Microchip Technology Inc. ...
Page 193
... BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION Less than T SDA pulled low by other master. SDA Reset BRG and assert SDA. SCL SEN BCLIF S SSPIF 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 SDA = 0, SCL = BRG BRG SCL = 0 before SDA = 0, bus collision occurs. Set BCLIF. SDA = 0, SCL = 1 ...
Page 194
... Repeated Start condition is complete. Sample SDA when SCL goes high. If SDA = 0, set BCLIF and release SDA and SCL. Cleared in software T T BRG BRG 2003 Microchip Technology Inc. ‘0’ ‘0’ Interrupt cleared in software ‘0’ ...
Page 195
... SCL PEN BCLIF P SSPIF 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 The Stop condition begins with SDA asserted low. When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), the Baud Rate Generator is loaded with SSPADD<6:0> ...
Page 196
... PIC18F2220/2320/4220/4320 NOTES: DS39599C-page 194 2003 Microchip Technology Inc. ...
Page 197
... TRISC<7> bit must be set (= 1) • TRISC<6> bit must be cleared (= 0) Register 18-1 shows the Transmit Status and Control register (TXSTA) and Register 18-2 shows the Receive Status and Control register (RCSTA). 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 18.1 Asynchronous Operation in Power Managed Modes ...
Page 198
... Value at POR DS39599C-page 196 R/W-0 R/W-0 U-0 TX9 TXEN SYNC W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R/W-0 R-1 R/W-0 — BRGH TRMT TX9D bit Bit is unknown 2003 Microchip Technology Inc. ...
Page 199
... Overrun error (can be cleared by clearing bit CREN overrun error bit 0 RX9D: 9th bit of Received Data This can be address/data bit or a parity bit and must be calculated by user firmware. Legend Readable bit - n = Value at POR 2003 Microchip Technology Inc. PIC18F2220/2320/4220/4320 R/W-0 R/W-0 R/W-0 RX9 SREN CREN ...
Page 200
... Bit 1 SYNC — BRGH TRMT CREN ADDEN FERR OERR BRGH = 1 (High Speed) /( 1)) OSC N/A Value on Value on Bit 0 all other POR, BOR Resets TX9D 0000 -010 0000 -010 RX9D 0000 -00x 0000 -00x 0000 0000 0000 0000 2003 Microchip Technology Inc. ...