PIC18F4220-I/P Microchip Technology Inc., PIC18F4220-I/P Datasheet - Page 28
![no-image](/images/manufacturer_photos/0/4/440/microchip_technology_inc__sml.jpg)
PIC18F4220-I/P
Manufacturer Part Number
PIC18F4220-I/P
Description
Microcontroller; 4 KB Flash; 512 RAM; 256 EEPROM; 36 I/O; 40-Pin-PDIP
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F4220-IP.pdf
(388 pages)
Specifications of PIC18F4220-I/P
A/d Inputs
13-Channel, 10-Bit
Comparators
2
Cpu Speed
10 MIPS
Eeprom Memory
256 Bytes
Input Output
36
Interface
I2C/SPI/UART/USART
Memory Type
Flash
Number Of Bits
8
Package Type
40-pin PDIP
Programmable Memory
4K Bytes
Ram Size
512 Bytes
Speed
40 MHz
Timers
1-8-bit, 3-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F4220-I/PT
Manufacturer:
SST
Quantity:
1 150
Company:
Part Number:
PIC18F4220-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
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- Download datasheet (7Mb)
PIC18F2220/2320/4220/4320
REGISTER 2-2:
DS39599C-page 26
bit 7
bit 6-4
bit 3
bit 2
bit 1-0
OSCCON REGISTER
bit 7
IDLEN: Idle Enable bit
1 = Idle mode enabled; CPU core is not clocked in power managed modes
0 = Run mode enabled; CPU core is clocked in power managed modes
IRCF2:IRCF0: Internal Oscillator Frequency Select bits
111 = 8 MHz (8 MHz source drives clock directly)
110 = 4 MHz
101 = 2 MHz
100 = 1 MHz
011 = 500 kHz
010 = 250 kHz
001 = 125 kHz
000 = 31 kHz (INTRC source drives clock directly)
OSTS: Oscillator Start-up Time-out Status bit
1 = Oscillator start-up time-out timer has expired; primary oscillator is running
0 = Oscillator start-up time-out timer is running; primary oscillator is not ready
IOFS: INTOSC Frequency Stable bit
1 = INTOSC frequency is stable
0 = INTOSC frequency is not stable
SCS1:SCS0: System Clock Select bits
1x = Internal oscillator block (RC modes)
01 = Timer1 oscillator (Secondary modes)
00 = Primary oscillator (Sleep and PRI_IDLE modes)
Legend:
R = Readable bit
- n = Value at POR
IDLEN
R/W-0
Note 1: Depends on state of IESO bit in Configuration Register 1H.
2: SCS0 may not be set while T1OSCEN (T1CON<3>) is clear.
IRCF2
R/W-0
R/W-0
IRCF1
W = Writable bit
‘1’ = Bit is set
R/W-0
IRCF0
(2)
(1)
OSTS
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R
(1)
IOFS
R-0
2003 Microchip Technology Inc.
x = Bit is unknown
R/W-0
SCS1
R/W-0
SCS0
bit 0
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