PIC16F636-I/P Microchip Technology Inc., PIC16F636-I/P Datasheet - Page 129

• Manufacturer Part Number: PIC16F636-I/P
• Description: 14 PIN, 3.5 KB FLASH, 128 RAM, 12 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F636-I/P

• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 12
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 14-pin PDIP
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Speed: 20 MHz
• Timers: 1-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

12.12 Power-Down Mode (Sleep)
The Power-down mode is entered by executing a
SLEEP instruction.
If the Watchdog Timer is enabled:
• WDT will be cleared but keeps running.
• PD bit in the Status register is cleared.
• TO bit is set.
• Oscillator driver is turned off.
• I/O ports maintain the status they had before
For lowest current consumption in this mode, all I/O pins
should be either at V
drawing current from the I/O pin and the comparators
and CV
impedance inputs should be pulled high or low externally
to avoid switching currents caused by floating inputs.
The T0CKI input should also be at V
current consumption. The contribution from on-chip
pull-ups on PORTA should be considered.
The MCLR pin must be at a logic high level.
12.12.1
The device can wake-up from Sleep through one of the
following events:
1.
2.
3.
The first event will cause a device Reset. The two latter
events are considered a continuation of program
execution. The TO and PD bits in the Status register
can be used to determine the cause of device Reset.
The PD bit, which is set on power-up, is cleared when
Sleep is invoked. TO bit is cleared if WDT wake-up
occurred.
The following peripheral interrupts can wake the device
from Sleep:
1.
2.
3.
4.
5.
© 2005 Microchip Technology Inc.
SLEEP was executed (driving high, low or
high-impedance).
Note 1: It should be noted that a Reset generated
External Reset input on MCLR pin.
Watchdog Timer wake-up (if WDT was enabled).
Interrupt from RA2/INT pin, PORTA change or a
peripheral interrupt.
TMR1 interrupt. Timer1 must be operating as an
asynchronous counter.
Special event trigger (Timer1 in Asynchronous
mode using an external clock).
EEPROM write operation completion.
Comparator output changes state.
Interrupt-on-change.
REF
2: The Analog Front-End (AFE) section in
WAKE-UP FROM SLEEP
should be disabled. I/O pins that are high-
by a WDT time-out does not drive MCLR
pin low.
the PIC16F639 device is independent of
the microcontroller’s power-down mode
(Sleep). See Section 11.32.2.3 “Sleep
Command” for AFE’s Sleep mode.
DD
or V
SS
, with no external circuitry
DD
or V
SS
for lowest
PIC12F635/PIC16F636/639
Preliminary
6.
Other peripherals cannot generate interrupts, since
during Sleep, no on-chip clocks are present.
When the SLEEP instruction is being executed, the next
instruction (PC + 1) is prefetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up is
regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
instruction after the SLEEP instruction. If the GIE bit is
set (enabled), the device executes the instruction after
the SLEEP instruction, then branches to the interrupt
address (0004h). In cases where the execution of the
instruction following SLEEP is not desirable, the user
should have a NOP after the SLEEP instruction.
The WDT is cleared when the device wakes up from
Sleep, regardless of the source of wake-up.
12.12.2
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
• If the interrupt occurs before the execution of a
• If the interrupt occurs during or after the
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes. To
determine whether a SLEEP instruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
To ensure that the WDT is cleared, a CLRWDT instruction
should be executed before a SLEEP instruction.
Note:
Note:
SLEEP instruction, the SLEEP instruction will
complete as a NOP. Therefore, the WDT and WDT
prescaler and postscaler (if enabled) will not be
cleared, the TO bit will not be set and the PD bit
will not be cleared.
execution of a SLEEP instruction, the device will
immediately wake-up from Sleep. The SLEEP
instruction will be completely executed before the
wake-up. Therefore, the WDT and WDT prescaler
and postscaler (if enabled) will be cleared, the TO
bit will be set and the PD bit will be cleared.
External Interrupt from INT pin.
If the global interrupts are disabled (GIE is
cleared), but any interrupt source has both
its interrupt enable bit and the corresponding
interrupt flag bits set, the device will
immediately wake-up from Sleep. The
SLEEP instruction is completely executed.
If WUR is enabled (WURE = 0 in
Configuration Word), then the Wake-up
Reset module will force a device Reset.
WAKE-UP USING INTERRUPTS
DS41232B-page 127