PIC16F883-I/ML Microchip Technology Inc., PIC16F883-I/ML Datasheet - Page 35
PIC16F883-I/ML
Manufacturer Part Number
PIC16F883-I/ML
Description
28 PIN, 7KB FLASH, 256 RAM, 25 I/O, QFN
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC16F883-IML.pdf
(328 pages)
Specifications of PIC16F883-I/ML
A/d Inputs
11-Channel, 10-Bit
Comparators
2
Cpu Speed
5 MIPS
Eeprom Memory
256 Bytes
Frequency
20 MHz
Input Output
24
Interface
I2C/SPI/USART
Memory Type
Flash
Number Of Bits
8
Package Type
28-pin QFN
Programmable Memory
7K Bytes
Ram Size
256 Bytes
Resistance, Drain To Source On
Bytes
Serial Interface
MSSP or EUSART
Speed
20 MHz
Timers
2-8-bit, 1-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
Available stocks
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Part Number
Manufacturer
Quantity
Price
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Part Number:
PIC16F883-I/ML
Manufacturer:
MICROCHIP
Quantity:
1 200
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2.2.2.5
The PIE2 register contains the interrupt enable bits, as
shown in Register 2-5.
REGISTER 2-5:
© 2008 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
OSFIE
R/W-0
PIE2 Register
OSFIE: Oscillator Fail Interrupt Enable bit
1 = Enables oscillator fail interrupt
0 = Disables oscillator fail interrupt
C2IE: Comparator C2 Interrupt Enable bit
1 = Enables Comparator C2 interrupt
0 = Disables Comparator C2 interrupt
C1IE: Comparator C1 Interrupt Enable bit
1 = Enables Comparator C1 interrupt
0 = Disables Comparator C1 interrupt
EEIE: EEPROM Write Operation Interrupt Enable bit
1 = Enables EEPROM write operation interrupt
0 = Disables EEPROM write operation interrupt
BCLIE: Bus Collision Interrupt Enable bit
1 = Enables Bus Collision interrupt
0 = Disables Bus Collision interrupt
ULPWUIE: Ultra Low-Power Wake-up Interrupt Enable bit
1 = Enables Ultra Low-Power Wake-up interrupt
0 = Disables Ultra Low-Power Wake-up interrupt
Unimplemented: Read as ‘0’
CCP2IE: CCP2 Interrupt Enable bit
1 = Enables CCP2 interrupt
0 = Disables CCP2 interrupt
R/W-0
C2IE
PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2
W = Writable bit
‘1’ = Bit is set
R/W-0
C1IE
PIC16F882/883/884/886/887
R/W-0
EEIE
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
BCLIE
Note:
Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
ULPWUIE
R/W-0
x = Bit is unknown
U-0
—
DS41291E-page 33
CCP2IE
R/W-0
bit 0
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