PIC18F2320-I/SO Microchip Technology Inc., PIC18F2320-I/SO Datasheet - Page 190

• Manufacturer Part Number: PIC18F2320-I/SO
• Description: Microcontroller; 8 KB Flash; 512 RAM; 256 EEPROM; 25 I/O; 28-Pin-SOIC
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F2320-I/SO

• A/d Inputs: 10-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 25
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SOIC
• Programmable Memory: 8K Bytes
• Ram Size: 512 Bytes
• Speed: 20 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F2220/2320/4220/4320
17.4.12
An Acknowledge sequence is enabled by setting the
Acknowledge
(SSPCON2<4>). When this bit is set, the SCL pin is
pulled low and the contents of the Acknowledge data bit
are presented on the SDA pin. If the user wishes to gen-
erate an Acknowledge, then the ACKDT bit should be
cleared. If not, the user should set the ACKDT bit before
starting an Acknowledge sequence. The Baud Rate
Generator then counts for one rollover period (T
the SCL pin is deasserted (pulled high). When the SCL
pin is sampled high (clock arbitration), the Baud Rate
Generator counts for T
low. Following this, the ACKEN bit is automatically
cleared, the Baud Rate Generator is turned off and the
MSSP module then goes into Idle mode (Figure 17-23).
17.4.12.1
If the user writes the SSPBUF when an Acknowledge
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
FIGURE 17-23:
FIGURE 17-24:
DS39599C-page 188
ACKNOWLEDGE SEQUENCE TIMING
WCOL Status Flag
Note: T
Note: T
Sequence
SSPIF
SCL
SDA
Acknowledge sequence starts here,
SDA
SCL
Write to SSPCON2,
Falling edge of
9th clock
BRG
ACKNOWLEDGE SEQUENCE WAVEFORM
STOP CONDITION RECEIVE OR TRANSMIT MODE
BRG
BRG
Set SSPIF at the end
of receive
. The SCL pin is then pulled
= one Baud Rate Generator period.
ACK
= one Baud Rate Generator period.
ACKEN = 1, ACKDT = 0
Enable
set PEN
write to SSPCON2,
bit,
8
D0
T
T
BRG
BRG
SDA asserted low before rising edge of clock
to setup Stop condition
BRG
ACKEN
) and
T
SCL brought high after T
BRG
Cleared in
software
T
BRG
P
ACK
SCL = 1 for T
after SDA sampled high. P bit (SSPSTAT<4>) is set.
T
17.4.13
A Stop bit is asserted on the SDA pin at the end of a
receive/transmit by setting the Stop Sequence Enable
bit, PEN (SSPCON2<2>). At the end of a receive/
transmit, the SCL line is held low after the falling edge
of the ninth clock. When the PEN bit is set, the master
will assert the SDA line low. When the SDA line is sam-
pled low, the Baud Rate Generator is reloaded and
counts down to 0. When the Baud Rate Generator
times out, the SCL pin will be brought high and one
T
SDA pin will be deasserted. When the SDA pin is sam-
pled high while SCL is high, the P bit (SSPSTAT<4>) is
set. A T
bit is set (Figure 17-24).
17.4.13.1
If the user writes the SSPBUF when a Stop sequence
is in progress, then the WCOL bit is set and the con-
tents of the buffer are unchanged (the write doesn’t
occur).
BRG
BRG
T
BRG
9
Set SSPIF at the end
of Acknowledge sequence
(Baud Rate Generator rollover count) later, the
BRG
PEN bit (SSPCON2<2>) is cleared by
hardware and the SSPIF bit is set
BRG
BRG
STOP CONDITION TIMING
, followed by SDA = 1 for T
later, the PEN bit is cleared and the SSPIF
WCOL Status Flag
ACKEN automatically cleared
 2003 Microchip Technology Inc.
Cleared in software
BRG