PIC18F2320-I/SO Microchip Technology Inc., PIC18F2320-I/SO Datasheet - Page 75

• Manufacturer Part Number: PIC18F2320-I/SO
• Description: Microcontroller; 8 KB Flash; 512 RAM; 256 EEPROM; 25 I/O; 28-Pin-SOIC
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F2320-I/SO

• A/d Inputs: 10-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 25
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SOIC
• Programmable Memory: 8K Bytes
• Ram Size: 512 Bytes
• Speed: 20 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

REGISTER 6-1:
 2003 Microchip Technology Inc.
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
EECON1 REGISTER
Legend:
R = Readable bit
- n = Value at POR ‘1’ = Bit is set
bit 7
EEPGD: Flash Program or Data EEPROM Memory Select bit
1 = Access program Flash memory
0 = Access data EEPROM memory
CFGS: Flash Program/Data EE or Configuration Select bit
1 = Access configuration registers
0 = Access program Flash or data EEPROM memory
Unimplemented: Read as ‘0’
FREE: Flash Row Erase Enable bit
1 = Erase the program memory row addressed by TBLPTR on the next WR command
0 = Perform write only
WRERR: EEPROM Error Flag bit
1 = A write operation was prematurely terminated (any Reset during self-timed programming)
0 = The write operation completed normally
WREN: Write Enable bit
1 = Allows erase or write cycles
0 = Inhibits erase or write cycles
WR: Write Control bit
1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write
0 = Write cycle completed
RD: Read Control bit
1 = Initiates a memory read (Read takes one cycle. RD is cleared in hardware. The RD bit can
0 = Read completed
EEPGD
R/W-x
Note:
(cleared by completion of erase operation – TBLPTR<5:0> are ignored)
cycle. (The operation is self-timed and the bit is cleared by hardware once write is
complete. The WR bit can only be set (not cleared) in software.)
only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1.)
When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows
tracing of the error condition.
CFGS
R/W-x
S = Settable only
PIC18F2220/2320/4220/4320
U-0
—
R/W-0
FREE
U = Unimplemented bit, read as ‘0’ W = Writable bit
‘0’ = Bit is cleared
WRERR
R/W-x
WREN
R/W-0
R/S-0
WR
x = Bit is unknown
DS39599C-page 73
R/S-0
RD
bit 0