ADM560JRS Analog Devices Inc, ADM560JRS Datasheet - Page 5

• Manufacturer Part Number: ADM560JRS
• Description: IC TXRX RS232 4:5 3.3V LP 28SSOP
• Manufacturer: Analog Devices Inc
• Type: Transceiverr

Specifications of ADM560JRS

• Rohs Status: RoHS non-compliant
• Number Of Drivers/receivers: 4/5
• Protocol: RS232
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 28-SSOP

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 3. Pin Function Descriptions
Pin No.
2, 3, 1, 28
9, 4, 27, 23, 18
8, 5, 26, 22, 19
7, 6, 20, 21
10
11
12, 14
13
15, 16
17
24
25
Table 4. ADM560/ADM561 Enable and Shutdown Control
Normal Operation
Shutdown Mode
Mnemonic
T1
GND
V
C1+, C1−
V+
C2+, C2−
V−
EN/EN
SHDN/SHDN
T1
R1
R1
CC
OUT
IN
OUT
IN
to T4
to R5
to T4
to R5
R2
R1
IN
T3
T1
T2
IN
OUT
GND
R2
R1
OUT
T2
T1
V
C1+
C1–
OUT
OUT
OUT
OUT
OUT
Figure 2.ADM560 Pin Configuration
V+
CC 11
IN
IN
IN
IN
ADM560
SHDN = 1
EN = 1; receivers active
EN = 0; receivers inactive
SHDN = 0
EN = 1; Receiver R1 to Receiver R3 inactive
EN = 1; Receiver R4 and Receiver R5 active
EN = 0; Receiver R1 to Receiver R5 inactive
10
12
13
14
1
2
3
4
5
6
7
8
9
Description
Transmitter (Driver) Outputs. Typically ±6 V.
Receiver Inputs. These inputs accept RS-232 signal levels. An internal 5 kΩ pull-down resistor to GND is
connected on each of these inputs.
Receiver Outputs. These are 3 V logic levels.
Transmitter (Driver) Inputs. These inputs accept 3 V or 5 V logic levels. An internal 400 kΩ pull-up resistor
to V
Ground Pin. Must be connected to 0 V.
Power Supply Input 3.3 V ± 10%.
External Capacitor 1 is connected between these pins.
Internally Generated Positive Supply. +6.6 V nominal.
External Capacitor 2 is connected between these pins.
Internally Generated Negative Supply. −6.6 V nominal.
Receiver Enable. EN, active high on ADM560. EN, active low on ADM561. Refer to Table 4.
Shutdown Control. SHDN, active low on ADM560. SHDN, active high on ADM561. Refer to Table 4.
(Not to Scale)
ADM560
TOP VIEW
CC
is connected on each input.
28
27
26
25
24
23
22
21
20
19
18
17
16
15
T4
R3
R3
SHDN
EN
R4
R4
T4
T3
R5
R5
V–
C2–
C2+
OUT
IN
IN
IN
OUT
IN
OUT
OUT
IN
Rev. B | Page 5 of 12
R2
R1
T3
T1
T2
GND
R2
R1
T2
T1
V
C1+
C1–
OUT
OUT
OUT
OUT
OUT
Figure 3. ADM561 Pin Configuration
V+
CC 11
IN
IN
IN
IN
10
12
13
14
1
2
3
4
5
6
7
8
9
(Not to Scale)
ADM561
TOP VIEW
28
27
26
25
24
23
22
21
20
19
18
17
16
15
ADM561
SHDN = 0
EN = 0; receivers active
EN = 1; receivers inactive
SHDN = 1
EN = 0; receivers inactive
EN = 1; receivers inactive
T4
R3
R3
SHDN
EN
R4
R4
T4
T3
R5
R5
V–
C2–
C2+
OUT
IN
IN
IN
OUT
IN
OUT
OUT
IN
ADM560/ADM561