FM3204-G Ramtron, FM3204-G Datasheet - Page 11

• Manufacturer Part Number: FM3204-G
• Description: Supervisory Circuits 4K w/Pwr Mon WDT Bat Sw Pwr Fail
• Manufacturer: Ramtron

Specifications of FM3204-G

• Number Of Voltages Monitored: 4
• Monitored Voltage: 2.6 V or 2.9 V or 3.9 V or 4.4 V
• Output Type: Active Low or Bidirectional
• Manual Reset: Resettable
• Watchdog: Watchdog
• Battery Backup Switching: Backup
• Power-up Reset Delay (typ): 200 ms
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Supply Current (typ): 1500 uA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-14
• Minimum Operating Temperature: - 40 C
• Power Fail Detection: Yes
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Two-wire Interface
The FM32xx employs an industry standard two-wire
bus that is familiar to many users. This product is
unique since it incorporates two logical devices in
one chip. Each logical device can be accessed
individually. Although monolithic, it appears to the
system software to be two separate products. One is
a memory device. It has a Slave Address (Slave ID =
1010b) that operates the same as a stand-alone
memory device. The second device is a real-time
clock and processor companion which have a unique
Slave Address (Slave ID = 1101b).
Start Condition
A Start condition is indicated when the bus master
drives SDA from high to low while the SCL signal is
high. All read and write transactions begin with a
Start condition. An operation in progress can be
aborted by asserting a Start condition at any time.
Aborting an operation using the Start condition will
ready the FM32xx for a new operation.
If the power supply drops below the specified V
during operation, any 2-wire transaction in progress
will be aborted and the system must issue a Start
condition prior to performing another operation.
Stop Condition
A Stop condition is indicated when the bus master
drives SDA from low to high while the SCL signal is
high. All operations must end with a Stop condition.
If an operation is pending when a stop is asserted,
the operation will be aborted. The master must have
control of SDA (not a memory read) in order to
assert a Stop condition.
Data/Address Transfer
All data transfers (including addresses) take place
while the SCL signal is high. Except under the two
conditions described above, the SDA signal should
not change while SCL is high.
Rev. 3.1
July 2010
SDA
SCL
(Master)
Stop
(Master)
Start
Figure 7. Data Transfer Protocol
TP
(Transmitter)
7
Data bits
By convention, any device that is sending data onto
the bus is the transmitter while the target device for
this data is the receiver. The device that is
controlling the bus is the master. The master is
responsible for generating the clock signal for all
operations. Any device on the bus that is being
controlled is a slave. The FM32xx is always a slave
device.
The bus protocol is controlled by transition states in
the SDA and SCL signals. There are four conditions:
Start, Stop, Data bit, and Acknowledge. The figure
below illustrates the signal conditions that specify
the four states. Detailed timing diagrams are shown
in the Electrical Specifications section.
Acknowledge
The Acknowledge (ACK) takes place after the 8
data bit has been transferred in any transaction.
During this state the transmitter must release the
SDA bus to allow the receiver to drive it. The
receiver drives the SDA signal low to acknowledge
receipt of the byte. If the receiver does not drive
SDA low, the condition is a No-Acknowledge
(NACK) and the operation is aborted.
The receiver might NACK for two distinct reasons.
First is that a byte transfer fails. In this case, the
NACK ends the current operation so that the part can
be addressed again. This allows the last byte to be
recovered in the event of a communication error.
Second and most common, the receiver does not
send an ACK to deliberately terminate an operation.
For example, during a read operation, the FM32xx
will continue to place data onto the bus as long as the
receiver sends ACKs (and clocks). When a read
operation is complete and no more data is needed,
the receiver must NACK the last byte. If the receiver
ACKs the last byte, this will cause the FM32xx to
attempt to drive the bus on the next clock while the
master is sending a new command such as a Stop.
6
(Transmitter)
Data bit
0
Acknowledge
(Receiver)
FM3204/16/64/256
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