PEB3086FV14XP Lantiq, PEB3086FV14XP Datasheet - Page 15

• Manufacturer Part Number: PEB3086FV14XP
• Manufacturer: Lantiq

Specifications of PEB3086FV14XP

• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

IOM-2 Interface
Monitor channel
programming
C/I channels
Layer 1 state machine
Layer 1 state machine
in software
Support of IDSL (144kBit/s) Provided
D-channel HDLC support
D-channel FIFO size
FW download support
HDLC support (B-channel)
FIFO size (B-channel)
Reset Signals
Data Sheet
ISAC-SX PEB 3086
Double clock (DCL),
bit clock (BCL),
serial data strobe 1 (SDS1)
serial data strobe 2 (SDS2)
Provided
(MON0, 1, 2, ..., 7)
CI0 (4bit),
CI1 (4/6bit)
With changes for
correspondence with the
actual ITU specification
Possible
(HDLC controller access,
SDS1/2 signals active)
D- and B-channel timeslots;
non-auto mode,
transparent mode 0-2,
extended transparent mode
64 bytes cyclic buffer per
direction with
programmable FIFO
thresholds
One B-channel controller
D- and B-channel timeslots;
non-auto mode,
transparent mode 0-2,
extended transparent mode
128 bytes cyclic buffer per
direction with
programmable FIFO
thresholds (8 or 16 bytes)
RES input signal
RSTO output signal
15
ISAC-S PEB 2086
Double clock (DCL),
bit clock (BCL),
serial data strobe (SDS)
Provided
(MON0 or 1)
CI0 (4bit),
CI1 (6bit)
Not possible
Not provided
D-channel timeslot;
auto mode,
non-auto mode,
transparent mode 1-3
2x32 bytes buffer per
direction
Not provided
Not provided
Not provided
RST input/output signal
PEB 3086
2003-01-30
ISAC-SX
Overview