PEB3086FV14XP Lantiq, PEB3086FV14XP Datasheet - Page 153

PEB3086FV14XP

Manufacturer Part Number
PEB3086FV14XP
Description
Manufacturer
Lantiq
Datasheet

Specifications of PEB3086FV14XP

Control Interface
HDLC
Lead Free Status / Rohs Status
Compliant
3.8.7
The cause of an interrupt related to the HDLC controllers is indicated in the ISTA register
by the ICD bit for D-channel and ICB for B-channel. These bits point to the different
interrupt sources of the HDLC controllers in the ISTAD and ISTAB registers. The
individual interrupt sources of the HDLC controllers during reception and transmission of
data are explained in
Figure 79
Each interrupt source in the ISTAD and ISTAB registers can selectively be masked by
setting the corresponding bit in MASKD/MASKB to “1”.
Data Sheet
MASK
TRAN
MOS
Interrupt
AUX
CIC
ICD
ICB
ST
HDLC Controller Interrupts
Interrupt Status Registers of the HDLC Controllers
TRAN
ISTA
MOS
AUX
ICB
CIC
ICD
Chapter 3.8.3.1
ST
MASKD
RME
XMR
RFO
XDU
RPF
XPR
or
D-channel
Chapter 3.8.4.1
153
ISTAD
RME
XMR
RFO
XPR
XDU
RPF
Description of Functional Blocks
respectively.
MASKB
RME
RFO
RPF
XPR
XDU
B-channel
3086_16.vsd
ISTAB
RME
RFO
XDU
RPF
XPR
PEB 3086
2003-01-30
ISAC-SX

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