PSB21150HV14XP Lantiq, PSB21150HV14XP Datasheet - Page 186

• Manufacturer Part Number: PSB21150HV14XP
• Manufacturer: Lantiq

Specifications of PSB21150HV14XP

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

CIX0
CIR1
4.1.19
Value after reset: FE
CODX0 ... C/I-Code 0 Transmit
Code to be transmitted in the C/I-channel 0. The code is only transmitted if the TIC bus
is occupied. If TIC bus is enabled but occupied by another device, only “1s” are
transmitted.
TBA2-0 ... TIC Bus Address
Defines the individual address for the IPAC-X on the IOM bus.This address is used to
access the C/I- and D-channel on the IOM interface.
Note: If only one device is liable to transmit in the C/I- and D-channels of the IOM it
BAC ... Bus Access Control
Only valid if the TIC-bus feature is enabled (MODED.DIM2-0).
If this bit is set, the IPAC-X will try to access the TIC-bus to occupy the C/I-channel even
if no D-channel frame has to be transmitted. It should be reset when the access has been
completed to grant a similar access to other devices transmitting in that IOM-channel.
Note: Access is always granted by default to the IPAC-X with TIC-Bus Address (TBA2-0,
4.1.20
Value after reset: FE
Data Sheet
CIR0 is not read, only the first and the last C/I code is made available in CIR0 at
the first and second read of that register, respectively.
should always be given the address value ’7’.
STCR register) ’7’, which has the lowest priority in a bus configuration.
7
7
CIX0 - Command/Indication Transmit 0
CIR1 - Command/Indication Receive 1
H
H
CODX0
CODR1
186
TBA2 TBA1 TBA0
Detailed Register Description
CICW CI1E
0
0
BAC
PSB/PSF 21150
2003-01-30
WR (2E)
IPAC-X
RD (2F)