MC145574APBR2 Freescale Semiconductor, MC145574APBR2 Datasheet - Page 58

• Manufacturer Part Number: MC145574APBR2
• Manufacturer: Freescale Semiconductor

Specifications of MC145574APBR2

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

6–12
BR15
OR15
OR6
OR7
OR8
OR9
6.8.5
6.9
NT
TE
All these registers are detailed in the following sections of this document: Section 8 for the nibble
registers, Section 9 for the byte registers, and Section 10 for the overlay registers.
SCP/GCI Register Differences
When configured for GCI direct mode of operation, the following register bits have different functionality
from SCP mode.
OR7(6)
This bit can be enabled only in GCI 1.536 MHz clock mode. This bit provides the availability of the
D channel on the S/T loop. “1” = Stop (no availability of the D channel) and “0” = Go (availability of
the D channel). Refer to Section 11.
OR8(0)
In GCI mode, the sleep mode is enabled by default. It can be disabled by writing to the register bit
(i.e., by writing a logic 1). This is opposite to operation of these bits in the SCP mode.
COMMAND INDICATE CHANNEL OPERATION
The command/indication (C/I) is intended to manage layer 1 procedures such as activation and deac-
tivation of the line, test loop control, and other additional control functions. C/I codes are four bits
in length and must be received for two consecutive GCI frames before they are acted upon.
The C/I channel bits are numbered bit 4 through bit 1, with bit 4 being the most significant bit. The
C/I channel command bits are transmitted starting with bit 4.
The command channel (COM) is an input to the device in the C/I channel of the GCI frame on the
D in pin.
The indicate channel (IND) is an output from the device in the GCI channel of the GCI frame on the
D out pin.
In both the COM and IND cases, the four–bit word is continually input or output until superceded by
another C/I channel word.
The command and indicate words used by the MC145574 device are defined in Table 6–8. This table
is fully compatible with the industry standard GCI specification.
Disable 3 V
Regulator
Register
Enabled
Register
TSA B1
Overlay
Overlay
Enable
Enable
(7)
(7)
Enable S/G Bit
Sleep Disable
Freescale Semiconductor, Inc.
TSA B2
S/G Bit
Enable
Enable
For More Information On This Product,
(6)
(6)
Disable XTAL
Go to: www.freescale.com
TSA D
Enable
Enable
Rev 5
Rev 5
TCLK
(5)
(5)
MC145574
Rev 4
Rev 4
(4)
(4)
D out Open
Rev 3
Rev 3
Drain
(3)
(3)
Force INFO 2
Mode Enable
Transmission
GCI Indirect
FIX Enable
Rev 2
Rev 2
(2)
(2)
Mode Enable
T3F8 Enable T3F6 Disable
Enable BCL
NT Terminal
Rev 1
Rev 1
CLK1
(1)
(1)
MOTOROLA
Disable
Rev 0
Sleep
Rev 0
CLK0
(0)
(0)