MC145574APBR2 Freescale Semiconductor, MC145574APBR2 Datasheet - Page 84

• Manufacturer Part Number: MC145574APBR2
• Manufacturer: Freescale Semiconductor

Specifications of MC145574APBR2

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

9–8
9.10
9.11
signals will be free–running (derived from the crystal). If the loop is active, these signals will be synchro-
nous to the inbound data. This bit is a read/write bit and is reset to 0 by application of either a software
or a hardware reset.
BR7(2) — IDL2 Clock Speed (LSB)
This bit is a read/write bit and is applicable to both NT and TE modes of operation. BR7(2), in conjunc-
tion with BR13(5), determines the IDL2 CLK frequency when operating in the IDL2 master mode.
BR7(2) is the LSB and BR13(5) is the MSB. The code corresponding to each IDL2 clock frequency
is shown in Table 9–4.
Application of either a hardware or a software reset will reset this bit to 0. Refer to Section 4 for a
more detailed description of this feature.
BR7(1) — NT: LAPD Polarity Control (NT Terminal Mode)
When the MC145574 is configured as a TE or an NT (Terminal Mode), this bit performs the “LAPD
Polarity Control” function. When this bit is 0, the active state of DREQUEST and DGRANT signals
is defined to be the logic 1 or high state. When this bit is 1, the active state of these signals is defined
to be the logic 0 or low state. This bit is a read/write bit and is reset to 0 by application of either a
hardware or software reset.
BR7(0) — NT: Activation Timer #2 Expired
When the MC145574 is configured as an NT, this bit performs the “Activation Timer #2 Expired” func-
tion. When this bit is 0, the NT–configured S/T transceiver uses a value of 50 ms for the Timer #2
value outlined in CCITT I.430, ETSI ETS 300012, and ANSI T1.605 (i.e., the device unambiguously
detects INFO 1). When this bit is 1, a value of 100 ms is used for the value of Timer #2. This bit is
a read/write bit and is reset to 0 by application of either a hardware or software reset.
BR8
The functions that were related to the IDL2 A/M FIFOs have been removed. Writing to these registers
will have no effect, and reading them will return 00H or any value that has been written to them. (No
register shown.)
BR9
BR9
RXSC2.1
TXSC2.1
TE: LAPD Polarity Control
TE: Not Applicable
NT:
TE:
(7)
Freescale Semiconductor, Inc.
For More Information On This Product,
RXSC2.2
TXSC2.2
BR13(5)
TE:
NT:
(6)
0
0
1
1
Go to: www.freescale.com
Table 9–4. IDL2 Clock Speed Codes
RXSC2.3
TXSC2.3
MC145574
TE:
NT:
(5)
BR7(2)
0
1
0
1
RXSC2.4
TXSC2.4
TE:
NT:
(4)
2.048 MHz
1.536 MHz
2.56 MHz
512 kHz
RXSC3.1
Rate
TXSC3.1
TE:
NT:
(3)
IDL2 CLK
RXSC3.2
TXSC3.2
Duty Cycle
NT:
TE:
(2)
53.3%
50%
50%
50%
RXSC3.3
TXSC3.3
NT:
TE:
(1)
MOTOROLA
TXSC3.4
RXSC3.4
NT:
TE:
(0)