PEB3086FV14NP Lantiq, PEB3086FV14NP Datasheet - Page 211
PEB3086FV14NP
Manufacturer Part Number
PEB3086FV14NP
Description
Manufacturer
Lantiq
Datasheet
1.PEB3086FV14NP.pdf
(262 pages)
Specifications of PEB3086FV14NP
Control Interface
HDLC
Lead Free Status / Rohs Status
Not Compliant
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ISTA
4.5
4.5.1
Value after reset: 00
For all interrupts in the ISTA register following logical states are applied:
0: Interrupt is not acitvated
1: Interrupt is acitvated
ICB, ICD ... HDLC Interrupt from B-channel or D-channel
An interrupt originated from the HDLC controllers of the B-channel or D-channel has
been recognized.
ST ... Synchronous Transfer
This interrupt is generated to enable the microcontroller to lock on to the IOM timing for
synchronous transfers. The source can be read from the STI register.
CIC ... C/I Channel Change
A change in C/I channel 0 or C/I channel 1 has been recognized. The actual value can
be read from CIR0 or CIR1.
AUX ... Auxiliary Interrupts
Signals an interrupt generated from external awake (pin EAW), watchdog timer overflow,
timer1, timer2 or from one of the interrupt input pins (INT0, INT1). The source can be
read from the auxiliary interrupt register AUXI.
TRAN ... Transceiver Interrupt
An interrupt originated in the transceiver interrupt status register (ISTATR) has been
recognized.
MOS ... MONITOR Status
A change in the MONITOR Status Register (MOSR) has occured.
Note: A read of the ISTA register clears none of the interrupts. They are only cleared by
Data Sheet
reading the corresponding status register.
7
Interrupt and General Configuration
ISTA - Interrupt Status Register
ICB
H
0
ST
CIC
211
AUX
TRAN MOS
Detailed Register Description
0
ICD
PEB 3086
2003-01-30
ISAC-SX
RD (60)
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