PEB3086FV14NP Lantiq, PEB3086FV14NP Datasheet - Page 227
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PEB3086FV14NP
Manufacturer Part Number
PEB3086FV14NP
Description
Manufacturer
Lantiq
Datasheet
1.PEB3086FV14NP.pdf
(262 pages)
Specifications of PEB3086FV14NP
Control Interface
HDLC
Lead Free Status / Rohs Status
Not Compliant
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TMB
LA … Low Byte Address Compare; significant only in non automodes 8 and 16 and
in transparent mode 2
The low byte address of a 2-byte address field, or the single address byte of a 1-byte
address field is compared with two programmable registers (RAL1, RAL2) and with the
group address (fixed value FF
0 … Group address has been recognized
1 … RAL1 or RAL2 has been recognized
Note: RSTAB corresponds to the last received HDLC frame; it is duplicated into RFIFOB
4.6.14
Value after reset: 00
TLP ... Test Loop
The TX path of layer-2 is internally connected with the RX path of layer-2. Data coming
from the layer 1 controller will not be forwarded to the layer 2 controller.
Data Sheet
for every frame (last byte of frame).
If several frames are contained in the RFIFOB the corresponding status
information for each frame should be evaluated from the FIFO contents (last byte)
as RSTAB only refers to last frame in the FIFO.
7
TMB -Test Mode Register B-Channel
0
H
0
0
H
)
0
227
0
0
Detailed Register Description
0
0
TLP
PEB 3086
2003-01-30
ISAC-SX
RD/WR
(79)
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