PEF24901HV22XT Lantiq, PEF24901HV22XT Datasheet - Page 11

• Manufacturer Part Number: PEF24901HV22XT
• Manufacturer: Lantiq

Specifications of PEF24901HV22XT

• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

List of Figures
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Data Sheet
DFE-T/ AFE 2nd Generation Chip Set . . . . . . . . . . . . . . . . . . . . . . . . . 14
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
16-Line Card Application with DELIC-PB Solution. . . . . . . . . . . . . . . . 18
Connecting Two AFE/DFE-T Chip Sets . . . . . . . . . . . . . . . . . . . . . . . . 19
Recommended Clocking Scheme for More Than Two
DFE-T/AFE Chip Sets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Block Diagram and Data Flow Diagram (DFE-T V2.2 + AFE V2.1) . . . 32
Clock Supply and Data Exchange between Master and Slave . . . . . . 33
Multiplexed Frame Structure of the IOM®-2 Interface . . . . . . . . . . . . . 35
Handshake Protocol with a 2-Byte Monitor Message/Response . . . . . 37
Abortion of Monitor Channel Transmission . . . . . . . . . . . . . . . . . . . . . 39
Interface to the Analog Front End . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Frame Structure on SDX/SDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Awake Procedure Initiated by the LT . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Awake Procedure Initiated by the NT . . . . . . . . . . . . . . . . . . . . . . . . . 54
State Diagram Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
LT State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Activation Initiated by Exchange . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Activation Initiated by TE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Activation with Repeater Initiated by LT. . . . . . . . . . . . . . . . . . . . . . . . 70
Activation with Repeater Initiated by TE . . . . . . . . . . . . . . . . . . . . . . . 71
Deactivation (Always Initiated by the Exchange) . . . . . . . . . . . . . . . . . 72
Activation of Loop#1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Activation of Loop#1A (Repeater) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Activation of Loop#2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Test Loopbacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Loopbacks Featured by Register LOOP . . . . . . . . . . . . . . . . . . . . . . . 80
DFE-T V2.2 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Input/Output Waveform for AC Tests . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
IOM®-2 Interface Timing (Double Clock Mode). . . . . . . . . . . . . . . . . 101
Boundary Scan Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
12
PEF 24901
2002-09-30
DFE-T
Page