PEF24901HV22XT Lantiq, PEF24901HV22XT Datasheet - Page 43

• Manufacturer Part Number: PEF24901HV22XT
• Manufacturer: Lantiq

Specifications of PEF24901HV22XT

• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

3.4
The DFE-T V2.2 features 6 general purpose I/O pins per line port. This way transparent
control of test relays and power feeding circuits is possible via the IOM
channel. Four of the six pins are outputs, two are inputs.
Setting Relay Driver Pins
Four relay driver output pins Dij (where i = 0, 1, 2, 3 denotes the line port no. and j = A,
B, C, D specifies the pin) are available per line port. The logic state of the four relay driver
outputs which are assigned to the same line port can be set by a single MON-8
command, called ’SETD’. The value is latched as long as no other SETD command with
different relay driver settings is received.
The state of the relay driver pins is not affected by any software reset (C/I= RES). The
state of all relay driver pins after hardware reset is „low“.
Reading Status Pins
Each line port owns two status pins ST
j = 0, 1 specifies the pin) whose logical value is reported in the associated Monitor
channel. Any signal change at one of the status pins ST1..4 causes automatically the
issue of a two-byte MON-8 message ’AST’ whose two least significant bits reflect the
status of pin STij.
However, this automatic mechanism is only enabled again, if the previous status pin
message has been transferred and acknowledged correctly according to the Monitor
channel handshake protocol. It takes the DFE-T V2.2 at least 8x IOM
to transmit the 2-byte MON-8 message. Thus, repeated changes within periods shorter
than 8x IOM
only the value of the last recent status change will be reported. Note that the MON-8
transfer time depends also on the reaction time (acknowledge by MR-bit) of the DFE-T
counterpart.
Besides this automatic report the DFE-T V2.2 will issue the status pin Monitor message
’AST’ upon the MON-8 request ’RST’ .
The ST
3.5
The 4B3T U-interface performs full duplex data transmission and reception at the U-
reference point according to ETSI TS102080 and FTZ 1TR 220. It applies the 4B3T
block code together with adaptive echo cancelling and equalization. Transmission
performance shall be such that it meets all ETSI and FTZ test loops with margin.
The U-interface is designed for data transmission on twisted pair wires in local telephone
loops with ISDN basic rate access and a user bit rate of 144 kbit/s.
Data Sheet
ij
pins have to be tied to either VDD or GND, if they are not used.
General Purpose I/Os
U-Transceiver Functions
®
-2 frames will overwrite the status pin register information. For this reason
ij
(where i = 0,1, 2, 3 denotes the line port no. and
44
Functional Description
®
-2 frames (1 ms)
PEF 24901
®
-2 Monitor
2002-09-30
DFE-T