A3PN030-ZQNG48I Actel, A3PN030-ZQNG48I Datasheet - Page 17

• Manufacturer Part Number: A3PN030-ZQNG48I
• Manufacturer: Actel

Table 2-4 •
V
2.7 V or less
3 V
3.3 V
3.6 V
Notes:
1. Based on reliability requirements at 85°C.
2. The duration is allowed at one out of six clock cycles. If the overshoot/undershoot occurs at one out of two
CCI
cycles, the maximum overshoot/undershoot has to be reduced by 0.15 V.
and VMV
I/O Power-Up and Supply Voltage Thresholds for Power-On Reset
(Commercial and Industrial)
Sophisticated power-up management circuitry is designed into every ProASIC
circuits ensure easy transition from the powered-off state to the powered-up state of the device.
The many different supplies can power up in any sequence with minimized current spikes or surges.
In addition, the I/O will be in a known state through the power-up sequence. The basic principle is
shown in
There are five regions to consider during power-up.
ProASIC3 I/Os are activated only if ALL of the following three conditions are met:
V
Ramping up: 0.6 V < trip_point_up < 1.2 V
Ramping down: 0.5 V < trip_point_down < 1.1 V
V
Ramping up: 0.6 V < trip_point_up < 1.1 V
Ramping down: 0.5 V < trip_point_down < 1 V
V
specifically built-in hysteresis prevents undesirable power-up oscillations and current surges. Note
the following:
PLL Behavior at Brownout Condition
Actel recommends using monotonic power supplies or voltage regulators to ensure proper power-
up behavior. Power ramp-up should be monotonic at least until V
activation levels. The V
for more details).
When PLL power supply voltage and/or V
0.25 V), the PLL output lock signal goes low and/or the output clock is lost. Refer to the
Power-Up/-Down Behavior of Low-Power Flash Devices
on clock and lock recovery.
Overshoot and Undershoot Limits
CC
CCI
CC
1. V
2. V
3. Chip is in the operating mode.
•
•
Trip Point:
and V
Trip Point:
During programming, I/Os become tristated and weakly pulled up to V
JTAG supply, PLL power supplies, and charge pump V
behavior.
CC
CCI
Figure 2-1 on page
CCI
and V
> V
ramp-up trip points are about 100 mV higher than ramp-down trip points. This
CC
Average V
CCI
Duration as a Percentage of Clock Cycle
– 0.75 V (typical)
are above the minimum specified trip points
CC
CCI
activation level is specified as 1.1 V worst-case (see
–GND Overshoot or Undershoot
2-4.
1
10%
10%
10%
10%
5%
5%
5%
5%
A dv a n c e v 0. 2
CC
levels drop below the V
ProASIC3 nano DC and Switching Characteristics
chapter of the handbook for information
2
PUMP
(Figure 2-1 on page
CC
supply have no influence on I/O
and V
CC
Maximum Overshoot/
brownout levels (0.75 V ±
CCPLLX
Figure 2-1 on page 2-4
Undershoot
CCI
.
1.49 V
1.19 V
0.79 V
0.88 V
0.45 V
0.54 V
1.4 V
1.1 V
®
exceed brownout
3 device. These
2-4).
2
2 - 3