Si5327-EVB Silicon Laboratories Inc, Si5327-EVB Datasheet - Page 24

MCU, MPU & DSP Development Tools SI5327 EVAL BOARD

Si5327-EVB

Manufacturer Part Number
Si5327-EVB
Description
MCU, MPU & DSP Development Tools SI5327 EVAL BOARD
Manufacturer
Silicon Laboratories Inc
Datasheets

Specifications of Si5327-EVB

Processor To Be Evaluated
Si5327
Interface Type
I2C, SPI
Operating Supply Voltage
3.3 V
Lead Free Status / Rohs Status
 Details
Si5327
Reset value = 0100 0010
Reset value = 0000 0101
24
Register 2.
Register 3.
Name
Name
Type
Type
7:4
3:0
7:6
3:0
Bit
Bit
Bit
Bit
5
4
BWSEL_REG
Reserved
Reserved
SQ_ICAL
Reserved
DHOLD
Name
Name
D7
D7
[3:0]
Reserved
R
BWSEL_REG.
Selects nominal f3dB bandwidth for PLL. See DSPLLsim for settings. After BWSEL_REG
is written with a new value, an ICAL is required for the change to take effect.
DHOLD.
Forces the part into digital hold. This bit overrides all other manual and automatic clock
selection controls.
0: Normal operation.
1: Force digital hold mode. Overrides all other settings and ignores the quality of all of the
input clocks.
SQ_ICAL.
This bit determines if the output clocks will remain enabled or be squelched (disabled)
during an internal calibration. See Table 8 on page 20.
0: Output clocks enabled during ICAL.
1: Output clocks disabled during ICAL.
BWSEL_REG [3:0]
D6
D6
R/W
DHOLD
R/W
D5
D5
Preliminary Rev. 0.4
SQ_ICAL
R/W
D4
D4
Function
Function
D3
D3
R
R
D2
D2
R
R
D1
D1
R
R
D0
D0
R
R

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