EVAL-AD9838SDZ Analog Devices Inc, EVAL-AD9838SDZ Datasheet - Page 25

• Manufacturer Part Number: EVAL-AD9838SDZ
• Description: EVALUATION BOARD
• Manufacturer: Analog Devices Inc
• Series: -r

Specifications of EVAL-AD9838SDZ

• Main Purpose: Timing, Direct Digital Synthesis (DDS)
• Embedded: No
• Utilized Ic / Part: AD9838
• Primary Attributes: USB Powered or External Supply
• Secondary Attributes: SPI Interface
• Kit Application Type: Clock & Timing
• Application Sub Type: Clock Generator
• Kit Contents: Software CD, USB Cable
• Silicon Manufacturer: Analog Devices
• Silicon Core Number: AD9838
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

AD9838 to 68HC11/68L11 Interface
Figure 28 shows the serial interface between the AD9838 and
the 68HC11/68L11 microcontroller. The microcontroller is con-
figured as the master by setting the MSTR bit in the SPCR to 1.
This setting provides a serial clock on SCK; the MOSI output
drives the serial data line, SDATA. Because the microcontroller
does not have a dedicated frame sync pin, the FSYNC signal is
derived from a port line (PC7). The setup conditions for correct
operation of the interface are as follows:
•
•
When data is to be transmitted to the AD9838, the FSYNC line
(PC7) is taken low. Serial data from the 68HC11/68L11 is trans-
mitted in 8-bit bytes with only eight falling clock edges occurring
in the transmit cycle. Data is transmitted MSB first. To load data
into the AD9838, PC7 is held low after the first eight bits are
transferred, and a second serial write operation is performed to
the AD9838. Only after the second eight bits are transferred
should FSYNC be taken high again.
AD9838 to 80C51/80L51 Interface
Figure 29 shows the serial interface between the AD9838 and
the 80C51/80L51 microcontroller. The microcontroller is oper-
ated in Mode 0 so that TxD of the 80C51/80L51 drives SCLK of
the AD9838, and RxD drives the serial data line, SDATA. The
FSYNC signal is derived from a bit programmable pin on the
port (P3.3 is shown in Figure 29).
When data is to be transmitted to the AD9838, P3.3 is taken low.
The 80C51/80L51 transmits data in 8-bit bytes with only eight
falling SCLK edges occurring in each cycle. To load the remain-
ing eight bits to the AD9838, P3.3 is held low after the first eight
bits are transmitted, and a second write operation is initiated to
transmit the second byte of data. P3.3 is taken high following
the completion of the second write operation. SCLK should idle
high between the two write operations.
SCK idles high between write operations (CPOL = 0)
Data is valid on the SCK falling edge (CPHA = 1)
68HC11/68L11
Figure 28. 68HC11/68L11 to AD9838 Interface
MOSI
SCK
PC7
FSYNC
SDATA
SCLK
AD9838
Rev. A | Page 25 of 32
The 80C51/80L51 outputs the serial data in a format that has the
LSB first. The AD9838 accepts the MSB first (the four MSBs are
the control information, the next four bits are the address, and
the eight LSBs contain the data when writing to a destination
register). Therefore, the transmit routine of the 80C51/80L51
must take this into account and rearrange the bits so that the
MSB is output first.
AD9838 to DSP56002 Interface
Figure 30 shows the interface between the AD9838 and the
DSP56002. The DSP56002 is configured for normal mode asyn-
chronous operation with a gated internal clock (SYN = 0, GCK = 1,
SCKD = 1). The frame sync pin is generated internally (SC2 = 1),
the transfers are 16 bits wide (WL1 = 1, WL0 = 0), and the frame
sync signal frames the 16 bits (FSL = 0). The frame sync signal is
available on the SC2 pin, but it must be inverted before it is applied
to the AD9838. The interface to the DSP56000/DSP56001 is
similar to that of the DSP56002.
80C51/80L51
DSP56002
Figure 29. 80C51/80L51 to AD9838 Interface
Figure 30. DSP56002 to AD9838 Interface
P3.3
RXD
SCK
TXD
STD
SC2
FSYNC
SDATA
SCLK
FSYNC
SDATA
SCLK
AD9838
AD9838
AD9838