EVAL-AD9838SDZ Analog Devices Inc, EVAL-AD9838SDZ Datasheet - Page 3

• Manufacturer Part Number: EVAL-AD9838SDZ
• Description: EVALUATION BOARD
• Manufacturer: Analog Devices Inc
• Series: -r

Specifications of EVAL-AD9838SDZ

• Main Purpose: Timing, Direct Digital Synthesis (DDS)
• Embedded: No
• Utilized Ic / Part: AD9838
• Primary Attributes: USB Powered or External Supply
• Secondary Attributes: SPI Interface
• Kit Application Type: Clock & Timing
• Application Sub Type: Clock Generator
• Kit Contents: Software CD, USB Cable
• Silicon Manufacturer: Analog Devices
• Silicon Core Number: AD9838
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

SPECIFICATIONS
AVDD = DVDD = 2.3 V to 5.5 V, AGND = DGND = 0 V, T
otherwise noted.
Table 1.
Parameter
SIGNAL DAC SPECIFICATIONS
DDS SPECIFICATIONS
COMPARATOR
OUTPUT BUFFER
VOLTAGE REFERENCE
Resolution
Update Rate
I
V
V
Output Compliance
DC Accuracy
Dynamic Specifications
Spurious-Free Dynamic Range (SFDR)
Clock Feedthrough
Wake-Up Time
Input Voltage Range
Input Capacitance
Input High-Pass Cutoff Frequency
Input DC Resistance
Input Leakage Current
Output Rise/Fall Time
Output Jitter
Internal Reference
REFOUT Output Impedance
Reference TC
FSADJUST Voltage
OUT
OUT
OUT
A Grade
B Grade
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
Signal-to-Noise Ratio (SNR)
Total Harmonic Distortion (THD)
Wideband (0 to Nyquist)
Narrow-Band (±200 kHz)
A Grade
B Grade
Full Scale
Maximum
Minimum
A Grade
B Grade
A Grade
B Grade
A Grade
B Grade
A Grade
B Grade
1
2
3
4
Min
1.11
Typ
10
3.0
0.6
30
±1
±0.5
−63
−64
−64
−64
−68
−66
−97
−92
−68
−65
1
10
3
5
12
120
1
100
1.14
1.18
A
Rev. A | Page 3 of 32
= T
MIN
to T
Max
1
5
16
0.8
10
1.24
MAX
, R
SET
= 6.8 kΩ, R
Unit
Bits
mA
V
mV
LSB
ms
V p-p
ns
ps rms
kΩ
ppm/°C
MSPS
MSPS
V
LSB
dB
dB
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
pF
MHz
MΩ
μA
V
V
LOAD
= 200 Ω for IOUT and IOUTB, unless
Test Conditions/Comments
f
f
f
f
f
f
f
f
f
f
AC-coupled internally
Using a 15 pF load
3 MHz sine wave 0.6 V p-p
MCLK
MCLK
MCLK
MCLK
MCLK
MCLK
MCLK
MCLK
MCLK
MCLK
= 5 MHz, f
= 16 MHz, f
= 5 MHz, f
= 16 MHz, f
= 5 MHz, f
= 16 MHz, f
= 5 MHz, f
= 16 MHz, f
= 5 MHz, f
= 16 MHz, f
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
= f
= f
= f
= f
= reset
= f
= f
= f
= f
= reset
MCLK
MCLK
MCLK
MCLK
MCLK
MCLK
MCLK
MCLK
/4096
/4096
/50
/50
/4096
/4096
/50
/50
AD9838