S29GL512S10DHI020 Spansion Inc., S29GL512S10DHI020 Datasheet - Page 67

• Manufacturer Part Number: S29GL512S10DHI020
• Description: IC 512 MBIT, 3V, 100NS, 64-BALL FBGA, PAGE MODE
• Manufacturer: Spansion Inc.

Specifications of S29GL512S10DHI020

• Lead Free Status / Rohs Status: Supplier Unconfirmed

8.
8.1
8.2
February 11, 2011 S29GL_128S_01GS_00_01
Signal Protocols
Interface States
Power-Off with Hardware Data Protection
The following sections describe the host system interface signal behavior and timing for the 29GL-S family
flash devices.
Table 8.1
Legend:
L = V
H = V
X = either V
L/H = rising edge
H/L = falling edge
Valid = all bus signals have stable L or H level
Modified = valid state different from a previous valid state
Available = read data is internally stored with output driver controlled by OE#
Notes:
1. WE# and OE# can not be at V
2. Read with Output Disable is a read initiated with OE# High.
3. Automatic Sleep is a read/write operation where data has been driven on the bus for an extended period, without CE# going High and the
The memory is considered to be powered off when the core power supply (V
voltage (V
operation. This ensures that no spurious alteration of the memory content can occur during power transition.
During a power supply transition down to Power-Off, V
If V
state is entered and the EAC starts the Cold Reset Embedded Algorithm.
Power-Off with Hardware
Data Protection
Power-On (Cold) Reset
Hardware (Warm) Reset
Interface Standby
Automatic Sleep (Notes 1, 3)
Read with Output Disable
(Note 2)
Random Read
Page Read
Write
device internal logic has gone into standby mode to conserve power.
CC
D a t a
IL
IH
Interface State
goes below V
IL
describes the required value of each interface signal for each interface state.
LKO
or V
). When V
S h e e t
IH
RST
CC
(Min) then returns above V
≥ V
≥ V
≥ V
≥ V
≥ V
≥ V
≥ V
≥ V
( A d v a n c e
IL
< V
is below V
at the same time.
V
CC
CC
CC
CC
CC
CC
CC
CC
CC
LKO
min
min
min
min
min
min
min
min
GL-S MirrorBit
≥ V
≥ V
≥ V
≥ V
≥ V
≥ V
≥ V
≥ V
LKO
≤ V
≤ V
≤ V
≤ V
≤ V
≤ V
≤ V
≤ V
V
IO
IO
IO
IO
IO
IO
IO
IO
IO
CC
CC
CC
CC
CC
CC
CC
CC
, the entire memory array is protected against a program or erase
Table 8.1 Interface States
min
min
min
min
min
min
min
min
I n f o r m a t i o n )
RESET#
®
Family
X
X
H
H
H
H
H
H
L
RST
IO
(Min) to V
should remain less than or equal to V
CE#
X
X
X
H
L
L
L
L
L
CC
minimum, the Power-On Reset interface
OE#
X
X
X
X
X
H
H
L
L
CC
) drops below the lock-out
WE#
X
X
X
X
X
H
H
H
L
A
A
Modified
MAX
A3-A0
MAX
Valid
Valid
Valid
Valid
Valid
X
X
X
X
-A0
-A4
CC
.
DQ15-DQ0
Input Valid
Available
High-Z
High-Z
High-Z
High-Z
Output
High-Z
Output
Output
Valid
Valid
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