MM912H634CV1AER2 Freescale Semiconductor, MM912H634CV1AER2 Datasheet - Page 330
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MM912H634CV1AER2
Manufacturer Part Number
MM912H634CV1AER2
Description
64KS12 LIN2xLS/HS Isense
Manufacturer
Freescale Semiconductor
Series
-r
Datasheet
1.MM912G634CM1AE.pdf
(345 pages)
Specifications of MM912H634CV1AER2
Applications
Automotive
Core Processor
HCS12
Program Memory Type
FLASH (64 kB)
Controller Series
HCS12
Ram Size
6K x 8
Interface
LIN
Number Of I /o
-
Voltage - Supply
5.5 V ~ 27 V
Operating Temperature
-40°C ~ 105°C
Mounting Type
Surface Mount
Package / Case
48-LQFP Exposed Pad
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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A summary of the registers associated with the D2DI block is shown in
are given in the subsections that follow.
4.41.3.2
4.41.3.3
This register is used to enable and configure the interface width, the wait behavior and the frequency of the interface clock.
Freescale Semiconductor
Reset
Offset
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
Offset 0x0
W
R
D2DDATALO
D2DDATAHI
D2DADRLO
D2DADRHI
D2DSTAT0
D2DSTAT1
D2DEN
D2DCTL0
D2DCTL1
Register
Name
Register Definition
D2DI Control Register 0 (D2DCTL0)
7
0
D2DREGS
W
W
W
W
W
W
R
R
R
R
R
R
D2DNBLK
D2DCW
D2DBLK
6
0
D2DEN
ERRIF
D2DIE
D2DIF
RWB
Bit 7
Table 488. D2DI Control Register 0 (D2DCTL0)
Figure 117. D2DI Top Level Memory Map
D2DSWAI
ACKERF
D2DBSY
Non-blocking Write
D2DCW
MM912_634 Advance Information, Rev. 4.0
Table 487. D2DI Register Summary
256 Byte Window
256 Byte Window
Blocking Access
5
0
SZ8
8 Byte Control
6
0
Registers
= Unimplemented or Reserved
D2DSWAI
CNCLF
5
0
0
0
4
0
0
TIMEF
NBLK
Figure
4
0
0
0
DATA[15:8]
DATA[7:0]
ADR[7:0]
3
0
0
487. Detailed descriptions of the registers and bits
TERRF
3
0
0
0
2
0
0
PARF
TIMEOUT[3:0]
2
0
0
0
1
0
D2DCLKDIV[1:0]
Access: User read/write
PAR1
D2DCLKDIV[1:0]
1
0
0
PAR0
Bit 0
0
0
0
0
330
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