CS5532-BS Cirrus Logic Inc, CS5532-BS Datasheet

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CS5532-BS

Manufacturer Part Number
CS5532-BS
Description
IC, ADC, 24BIT, 3.84KSPS, SSOP-20
Manufacturer
Cirrus Logic Inc
Datasheet

Specifications of CS5532-BS

Resolution (bits)
24bit
Sampling Rate
3.84kSPS
Input Channel Type
Differential
Data Interface
3-Wire, Serial
Supply Current
13mA
Digital Ic Case Style
SSOP
No. Of Pins
20
Rohs Compliant
No

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Features
Preliminary Product Information
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com
Chopper Stabilized PGIA (Programmable
Gain Instrumentation Amplifier, 1x to 64x)
Delta-Sigma Analog-to-Digital Converter
Two or Four Channel Differential MUX
Scalable Input Span via Calibration
Scalable V
Simple three-wire serial interface
R/W Calibration Registers Per Channel
Selectable Word Rates: 6.25 to 3,840 Sps
Selectable 50 or 60 Hz Rejection
Power Supply Configurations
16-Bit and 24-Bit ADCs with Ultra Low Noise PGIA
6 nV/ Hz @ 0.1 Hz (No 1/f noise) at 64x
500 pA Input Current with Gains >1
Linearity Error: 0.0007% FS
Noise Free Resolution: Up to 23 bits
±5 mV to differential ±2.5V
SPI
Schmitt Trigger on Serial Clock (SCLK)
VA+ = +5 V; VA- = 0 V; VD+ = +3 V to +5 V
VA+ = +2.5 V; VA- = -2.5 V; VD+ = +3 V to +5 V
VA+ = +3 V; VA- = -3 V; VD+ = +3 V
®
and Microwire™ Compatible
AIN1+
AIN2+
AIN3+
AIN4+
AIN1-
AIN2-
AIN3-
AIN4-
REF
Input: Up to Analog Supply
VA+
VA-
(CS5533/34
SHOWN)
MUX
C1
PGIA
1,2,4,8,16
32,64
A0/GUARD
C2
LATCH
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
A1
VREF+
DIFFERENTIAL
4
MODULATOR
TH
ORDER
VREF-
Copyright
General Description
The CS5531/32/33/34 are highly integrated
to-Digital Converters (ADCs) which use charge-balance
techniques to achieve 16-bit (CS5531/33) and 24-bit
(CS5532/34) performance. The ADCs are optimized for
measuring low-level unipolar or bipolar signals in weigh
scale,
applications.
To accommodate these applications, the ADCs come as
either
(CS5533/34) devices and include a very low noise chop-
per-stabilized instrumentation amplifier (6 nV/ Hz @ 0.1
Hz) with selectable gains of 1×, 2×, 4×, 8×, 16×, 32×, and
64×. These ADCs also include a fourth order
lator followed by a digital filter which provides twenty
selectable output word rates of 6.25, 7.5, 12.5, 15, 25, 30,
50, 60, 100, 120, 200, 240, 400, 480, 800, 960, 1600,
1920, 3200, and 3840 Sps (MCLK = 4.9152 MHz).
To ease communication between the ADCs and a micro-
controller, the converters include a simple three-wire se-
rial interface which is SPI and Microwire compatible with
a Schmitt Trigger input on the serial clock (SCLK).
High dynamic range, programmable output rates, and
flexible power supply options makes these ADCs ideal
solutions
applications.
ORDERING INFORMATION
(All Rights Reserved)
See page 48
©
OSC1
GENERATOR
Cirrus Logic, Inc. 2002
PROGRAMMABLE
two-channel
SINC FIR FILTER
process
CLOCK
for
OSC2
weigh
VD+
CS5531/32/33/34
control,
SRAM/CONTROL
CALIBRATION
INTERFACE
(CS5531/32)
LOGIC
SERIAL
scale
scientific,
DGND
and
CS
SDI
SDO
SCLK
or
process
and
four-channel
DS289PP5
MAR ‘02
Analog-
medical
control
modu-
1

Related parts for CS5532-BS

CS5532-BS Summary of contents

Page 1

... General Description The CS5531/32/33/34 are highly integrated to-Digital Converters (ADCs) which use charge-balance techniques to achieve 16-bit (CS5531/33) and 24-bit (CS5532/34) performance. The ADCs are optimized for measuring low-level unipolar or bipolar signals in weigh scale, process applications. To accommodate these applications, the ADCs come as ...

Page 2

... TABLE OF CONTENTS 1. CHARACTERISTICS AND SPECIFICATIONS ..........................................................5 ANALOG CHARACTERISTICS..........................................................................5 TYPICAL RMS NOISE (NV), CS5531/32/33/34-AS ...........................................8 TYPICAL NOISE FREE RESOLUTION(BITS), CS5532/34-AS .........................8 TYPICAL RMS NOISE (NV), CS5532/34-BS .....................................................9 TYPICAL NOISE FREE RESOLUTION(BITS), CS5532/34-BS ......................... DIGITAL CHARACTERISTICS .................................................................. DIGITAL CHARACTERISTICS ..................................................................10 DYNAMIC CHARACTERISTICS ......................................................................11 ABSOLUTE MAXIMUM RATINGS ...................................................................11 SWITCHING CHARACTERISTICS ..................................................................12 2. GENERAL DESCRIPTION .......................................................................................14 2.1. Analog Input ....................................................................................................14 2 ...

Page 3

Filter Rate Select .................................................................................. 27 2.3.9. Configuration Register Descriptions ..................................................... 28 2.4. Setting up the CSRs for a Measurement ......................................................... 29 2.4.1. Channel-Setup Register Descriptions ................................................. 30 2.5. Calibration ....................................................................................................... 32 2.5.1. Calibration Registers ............................................................................ 32 2.5.2. Gain Register ...

Page 4

... Figure 25. Bridge with Series Resistors ..................................................................................44 LIST OF TABLES Table 1. Conversion Timing for Single Mode ..........................................................................36 Table 2. Conversion Timing for Continuous Mode ..................................................................37 Table 3. Command Byte Pointer .............................................................................................37 Table 4. Output Coding for 16-bit CS5531 and CS5533 .........................................................39 Table 5. Output Coding for 24-bit CS5532 and CS5534 .........................................................39 4 CS5531/32/33/34 DS289PP5 ...

Page 5

... TBD - CS5531/32/33/34 CS5531-AS/CS5533-AS Min Typ Max Unit - 0.0015 0.003 % Bits - 1 ±2 LSB - 2 4 LSB - 640 nV/° ppm - 16 62 ppm - 2 - ppm/°C CS5532-BS/CS5534-BS Min Typ Max Unit - 0.0007 0.0015 % Bits - 16 ±32 LSB - 32 64 LSB - 640 nV/° ppm - 16 62 ppm - 2 - ppm/° ...

Page 6

ANALOG CHARACTERISTICS Parameter Analog Input Common Mode + Signal on AIN+ or AIN-Bipolar/Unipolar Mode CVF Current on AIN+ or AIN- Input Current Noise Input Leakage for Mux when Off (at 25 °C) Off-Channel Mux Isolation Open Circuit Detect Current Common ...

Page 7

... Power is specified when the instrumentation amplifier (Gain 2) is on. Analog supply current is reduced by approximately 1/2 when the instrumentation amplifier is off (Gain = 1). 9. Tested with 100 mV change on VA+ or VA-. DS289PP5 (Continued) (See Notes 1 and 2.) CS5531/32/33/34-AS Max Min Typ A 500 - - 115 - - 115 - CS5531/32/33/34 CS5532/34-BS Max Min Typ Unit - 0 500 - µW - 115 - dB - 115 - dB 7 ...

Page 8

... Notes: 10. Wideband noise aliased into the baseband. Referred to the input. Typical values shown for 25 °C. 11. For Peak-to-Peak Noise multiply by 6.6 for all ranges and output rates. 12. Word rates and -3dB points with FRS = 0. When FRS = 1, word rates and -3dB points scale by 5/6. TYPICAL NOISE FREE RESOLUTION(BITS), CS5532/34-AS Output Word -3 dB Filter ...

Page 9

... Wideband noise aliased into the baseband. Referred to the input. Typical values shown for 25 °C. 17. For Peak-to-Peak Noise multiply by 6.6 for all ranges and output rates. 18. Word rates and -3dB points with FRS = 0. When FRS = 1, word rates and -3dB points scale by 5/6. TYPICAL NOISE FREE RESOLUTION(BITS), CS5532/34-BS Output Word -3 dB Filter ...

Page 10

V DIGITAL CHARACTERISTICS See Notes 2 and 21.) Parameter High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage A0 and A1, I Low-Level Output Voltage A0 and A1, I Input Leakage Current SDO 3-State Leakage Current Digital Output Pin ...

Page 11

DYNAMIC CHARACTERISTICS Parameter Modulator Sampling Rate Filter Settling Time to 1/2 LSB (Full Scale Step Input) Single Conversion mode (Notes 22, 23, and 24) Continuous Conversion mode, OWR < 3200 Sps Continuous Conversion mode, OWR 22. The ADCs use a ...

Page 12

SWITCHING CHARACTERISTICS ±10 ±5%;DGND = 0 V; Levels: Logic Logic 1 = VD+; C See Figures 1 and 2.) Parameter Master Clock Frequency External Clock or Crystal Oscillator Master Clock Duty Cycle Rise ...

Page 13

DS289PP5 Figure 1. SDI Write Timing (Not to ...

Page 14

... GENERAL DESCRIPTION The CS5531/32/33/34 are highly integrated alog-to-Digital Converters (ADCs) which use charge-balance techniques to achieve 16-bit (CS5531/33) and 24-bit (CS5532/34) performance. The ADCs are optimized for measuring low-level unipolar or bipolar signals in weigh scale, process control, scientific, and medical applications. To accommodate these applications, the ADCs ...

Page 15

... Voltage Noise Density Performance Figure 5 illustrates the measured voltage noise den- sity versus frequency from 0. CS5532-BS. The device was powered with ±2.5 V supplies, using 120 Sps OWR, the 64x gain range, bipolar mode, and with the input short bit enabled. ...

Page 16

DAC if desired. 2.2. Overview of ADC Register Structure and Operating Modes The CS5531/32/33/34 ADCs have an on-chip con- troller, which includes a number of user-accessible registers. ...

Page 17

Using the single conversion mode, an 8-bit com- mand word can be written into the serial port. The command includes pointer bits which ‘point’ 16-bit command in one of the Channel Setup Reg- isters which ...

Page 18

RS bit back to 0 insures the clearing of the RS bit in the event that a user does not write into the configuration register after the RS bit has been set. The RV bit in the ...

Page 19

Command Register Quick Reference D7(MSB ARA CS1 BIT NAME VALUE FUNCTION D7 Command Bit Access Registers as 0 Arrays, ARA 1 D5-D4 Channel Select Bits, 00 CS1-CS0 Read/Write, R/W ...

Page 20

Command Register Descriptions READ/WRITE ALL OFFSET CALIBRATION REGISTERS D7(MSB Function: These commands are used to access the offset registers as arrays. R/W (Read/Write) 0 Write to selected registers. 1 Read from selected registers. READ/WRITE ALL GAIN ...

Page 21

READ/WRITE INDIVIDUAL GAIN REGISTER D7(MSB Function These commands are used to access each gain register separately. CS1 - CS0 decode the reg- isters accessed. R/W (Read/Write) 0 Write to selected register. 1 Read from selected register. ...

Page 22

PERFORM CONVERSION D7(MSB CSRP2 Function: These commands instruct the ADC to perform either a single, fully-settled conversion or con- tinuous conversions on the physical input channel pointed to by the pointer bits (CSRP2 - CRSP0) in the ...

Page 23

PERFORM CALIBRATION D7(MSB CSRP2 Function: These commands instruct the ADC to perform a calibration on the physical input channel se- lected by the setup register which is chosen by the command byte pointer bits (CSRP2 - CSRP0). ...

Page 24

Serial Port Interface The CS5531/32/33/34’s serial interface consists of four control lines: CS, SDI, SDO, SCLK. Figure 7 details the command and data word timing. CS, Chip Select, is the control line which enables access to the serial port. ...

Page 25

... The default mode, “normal mode”, is entered after power is CS5531/32/33/34-AS versions typically consume 35 mW. The CS5532/34-BS versions typically consume 70 mW. The other two modes are referred to as the power save modes. They power down most of the analog portion of the chip and stop filter convolutions ...

Page 26

The RV bit is cleared after the configuration regis- ter is read. The on-chip registers are initialized to the following default states: Configuration Register: 00000000(H) Offset Registers: 00000000(H) Gain Registers: 01000000(H) Channel Setup Registers: 00000000(H) After reset, the RS bit ...

Page 27

MCLK VRS = Figure 9. ...

Page 28

Configuration Register Descriptions D31(MSB) D30 D29 D28 D27 PSS PDW RS RV D15 D14 D13 D12 D11 PSS (Power Save Select)[31] 0 Standby Mode (Oscillator active, allows quick power-up). 1 Sleep Mode (Oscillator inactive). ...

Page 29

Filter Rate Select, FRS[19] 0 Use the default output word rates. 1 Scale all output word rates and their corresponding filter characteristics by a factor of 5/6. NU (Not Used)[18:0] 0 Must always be logic 0. Reserved for future upgrades. ...

Page 30

Channel-Setup Register Descriptions CSR #1 Setup 1 Bits <127:112> #4 Setup 7 Bits <31:16> D31(MSB) D30 D29 D28 D27 CS1 CS0 D15 D14 D13 D12 D11 CS1 CS0 CS1-CS0 (Channel Select Bits) [31:30] ...

Page 31

U/B (Unipolar / Bipolar) [22] [6] 0 Select Bipolar mode. 1 Select Unipolar mode. OL1-OL0 (Output Latch Bits) [21:20] [5:4] The latch bits will be set to the logic state of these bits upon command word execution when the output ...

Page 32

Calibration Calibration is used to set the zero and gain slope of the ADC’s transfer function. The CS5531/32/33/34 offer both self calibration and system calibration. Note: After the ADCs are reset, they are functional and can perform measurements without ...

Page 33

Performing Calibrations To perform a calibration, the user must send a com- mand byte with its MSB=1, its pointer bits (CSRP2-CSRP0) set to address the desired Setup to calibrate, and the appropriate calibration bits (CC2- CC0) set to choose ...

Page 34

System Calibration For the system calibration functions, the user must supply the converters calibration signals which repre- sent ground and full scale. When a system offset cal- ibration is performed, a ground referenced signal must be applied to the ...

Page 35

ADC, and may prematurely halt the calibration cycle. For maximum accuracy, calibrations should be per- formed for both offset and gain (selected by chang- ing the G2-G0 bits ...

Page 36

SCLK transitions 40 times. After reading the data, the se- rial port returns to the command mode, where it waits for a new command to be issued. The single conversion mode ...

Page 37

FRS (WR3-WR0) Clock Cycles (First Conversion) 0 1010 17848 ± 1011 28088 ± 1100 48568 ± 0000 107434 ± 0001 205738 ± 0010 402346 ± 0011 795562 ± ...

Page 38

... SDO on only one ADC, (bring CS high for all but one part) and reading the data out of each part indi- vidually, before the next conversion data words are ready. An example of a synchronous system using two CS5532 parts is shown in Figure 15. 38 CS5531/32/33/34 CS5532 SDO ...

Page 39

... Unipolar Input Two's Voltage Complement >(VFS-1.5 LSB) FFFFFF >(VFS-1.5 LSB) 7FFF VFS-1.5 LSB 7FFF ------ 7FFE VFS/2-0.5 LSB 800000 0000 ------ FFFF +0.5 LSB 8001 ------ 8000 <(+0.5 LSB) 8000 Table 5. Output Coding for 24-bit CS5532 and CS5534 D26 D25 D24 D23 D10 D26 D25 ...

Page 40

Digital Filter The CS5531/32/33/34 have linear phase digital fil- ters which are programmed to achieve a range of output word rates (OWRs) as stated in the Channel- Setup Register Descriptions section. The ADCs use 5 a Sinc digital filter ...

Page 41

... CS5532 connected with ±2.5 V bipolar analog supplies and digital supply to measure ground referenced bipolar signals. Fig- ures 23 and 24 illustrate the CS5532 connected with ±3 V analog supplies and digital supply to measure ground referenced bipolar signals. Figure 25 illustrates alternate bridge configurations which can be measured with the converter ...

Page 42

... V Analog Supply - Figure 21. CS5532 Configured with a Single +5 V Supply 42 10 0.1 µ VA+ VD+ OSC2 18 VREF+ 17 VREF- 3 OSC1 CS5532 AIN1+ 2 AIN1- SDI 20 AIN2+ SDO 19 AIN2- SCLK DGND 6 16 CS5531/32/33/34 0.1 µF Optional 9 Clock Source 4.9152 MHz Serial Data 12 Interface 11 DS289PP5 ...

Page 43

... V Analog Supply - -2.5 V Analog Supply Figure 22. CS5532 Configured with ±2.5 V Analog Supplies +3 V Analog Supply - -3 V Analog Supply Figure 23. CS5532 Configured with ±3 V Analog Supplies DS289PP5 0.1 µ VA+ VD+ 18 OSC2 VREF+ 17 VREF- 3 OSC1 CS5532 AIN1+ 2 AIN1- SDI 20 AIN2+ SDO 19 AIN2- ...

Page 44

... V Analog Supply 2. Analog Supply Figure 24. CS5532 Configured for Thermocouple Measurement ( 0.1 µF 5 VA+ 1 AIN1+ 2 AIN1 CS5532 VREF+ 17 VREF- 20 AIN2+ Cold 19 AIN2- Junction Figure 25. Bridge with Series Resistors CS5531/32/33/34 0.1 µF 15 VD+ Optional 9 OSC2 Clock Source 4.9152 MHz 10 OSC1 Serial SDI ...

Page 45

Getting Started This A/D converter has several features. From a software programmer’s prospective, what should be done first? To begin, a 4.9152 MHz or 4.096 MHz crystal takes approximately start. To accommodate for this ...

Page 46

PIN DESCRIPTIONS DIFFERENTIAL ANALOG INPUT DIFFERENTIAL ANALOG INPUT AMPLIFIER CAPACITOR CONNECT AMPLIFIER CAPACITOR CONNECT POSITIVE ANALOG POWER NEGATIVE ANALOG POWER LOGIC OUTPUT (ANALOG)/GUARD LOGIC OUTPUT (ANALOG) MASTER CLOCK MASTER CLOCK DIFFERENTIAL ANALOG INPUT DIFFERENTIAL ANALOG INPUT DIFFERENTIAL ANALOG INPUT ...

Page 47

SDI - Serial Data Input. SDI is the input pin of the serial input port. Data will be input at a rate determined by SCLK. SDO - Serial Data Output. SDO is the serial data output. It will output a ...

Page 48

... The deviation of the mid-scale transition (111...111 to 000...000) from the ideal (1/2 LSB below the voltage on the AIN- pin). When in bipolar mode (U/B bit = 0). Units are in LSBs. 5. ORDERING GUIDE Model Number Bits Channels Linearity Error (Max) Temperature Range CS5531-AS 16 CS5533-AS 16 CS5532-AS 24 CS5532-BS 24 CS5534-AS 24 CS5534- 0.003 0.003% ...

Page 49

PACKAGE DRAWINGS 20 PIN SSOP PACKAGE DRAWING TOP VIEW DIM Notes: 1. “D” and “E1” are reference datums and do not included mold flash or ...

Page 50

PIN SSOP PACKAGE DRAWING TOP VIEW DIM Notes: 1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do ...

Page 51

Notes • ...

Page 52

...

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