CS5532-BS Cirrus Logic Inc, CS5532-BS Datasheet - Page 27

• Manufacturer Part Number: CS5532-BS
• Description: IC, ADC, 24BIT, 3.84KSPS, SSOP-20
• Manufacturer: Cirrus Logic Inc

Specifications of CS5532-BS

• Resolution (bits): 24bit
• Sampling Rate: 3.84kSPS
• Input Channel Type: Differential
• Data Interface: 3-Wire, Serial
• Supply Current: 13mA
• Digital Ic Case Style: SSOP
• No. Of Pins: 20
• Rohs Compliant: No

to limit drive currents to less than 20 A to reduce
self-heating of the chip. These outputs are powered
from VA+ and VA-. Their output voltage will be
limited to the VA+ voltage for a logic 1 and VA-
for a logic 0.
2.3.7. Offset and Gain Select
The Offset and Gain Select bit (OGS) is used to se-
lect the source of the calibration registers to use
when performing conversions and calibrations.
When the OGS bit is set to ‘0’, the offset and gain
registers corresponding to the desired physical
channel (CS1-CS0 in the selected Setup) will be ac-
cessed. When the OGS bit is set to ‘1’, the offset
and gain registers pointed to by the OG1-OG0 bits
in the selected Setup will be accessed. This feature
allows multiple calibration values (e.g. for different
gain settings) to be used on a single physical chan-
DS289PP5
Figure 9. Input Reference Model when VRS = 1
V
i = fV
n
os
V R E F
1 5 m V
os
C
VRS = 1; 1 V
f =
MCLK
16
2
C = 22 p F
C o a rs e
1
V
F in e
REF
2.5 V
nel without having to re-calibrate or manipulate the
calibration registers.
2.3.8. Filter Rate Select
The Filter Rate Select bit (FRS) modifies the output
word rates of the converter to allow either 50 Hz or
60 Hz rejection when operating from a 4.9152
MHz crystal. If FRS is cleared to logic 0, the word
rates and corresponding filter characteristics can be
selected (using the Channel Setup Registers) from
7.5, 15, 30, 60, 120, 240, 480, 960, 1920, or 3840
Sps when using a 4.9152 MHz clock. If FRS is set
to logic 1, the word rates and corresponding filter
characteristics scale by a factor of 5/6, making the
selectable word rates 6.25, 12.5, 25, 50, 100, 200,
400, 800, 1600, and 3200 Sps when using a 4.9152
MHz clock. When using other clock frequencies,
these selectable word rates will scale linearly with
the clock frequency that is used.
Figure 10. Input Reference Model when VRS = 0
V
i = fV
n
o s
V R E F
3 0 m V
os
C
VRS = 0; 2.5 V < V
f =
MCLK
16
CS5531/32/33/34
2
C = 1 1p F
C o a rs e
1
F in e
REF
VA+
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