CS5532-BS Cirrus Logic Inc, CS5532-BS Datasheet - Page 15

• Manufacturer Part Number: CS5532-BS
• Description: IC, ADC, 24BIT, 3.84KSPS, SSOP-20
• Manufacturer: Cirrus Logic Inc

Specifications of CS5532-BS

• Resolution (bits): 24bit
• Sampling Rate: 3.84kSPS
• Input Channel Type: Differential
• Data Interface: 3-Wire, Serial
• Supply Current: 13mA
• Digital Ic Case Style: SSOP
• No. Of Pins: 20
• Rohs Compliant: No

-40°C to +85°C (MCLK=4.9152 MHz). The com-
mon-mode plus signal range of the instrumentation
amplifier is (VA-) + 0.7 V to (VA+) - 1.7 V.
Figure 4 illustrates the input models for the ampli-
fiers. The dynamic input current for each of the
pins can be determined from the models shown.
Note:
2.1.1. Analog Input Span
The full scale input signal that the converter can dig-
itize is a function of the gain setting and the refer-
ence voltage connected between the VREF+ and
VREF- pins. The full scale input span of the convert-
er is ((VREF+) - (VREF-))/(GxA), where G is the
gain of the amplifier and A is 2 for VRS = 0, or A is
1 for VRS = 1. VRS is the Voltage Reference Select
bit, and must be set according to the differential volt-
age applied to the VREF+ and VREF- pins on the
part. See section 2.3.5 for more details.
DS289PP5
Figure 4. Input models for AIN+ and AIN- pins
V
i = fV
n
os
V
i = fV
n
os
The C=2.5pF and C = 16pF capacitors are for
input current modeling only. For physical
input capacitance see ‘Input Capacitance’
specification under Analog Characteristics.
AIN
1 mV
os
AIN
20 mV
os
C
Gain = 2, 4, 8, 16, 32, 64
C
f =
f =
Gain = 1
MCLK
MCLK
128
16
C =12.5 pF
1
C = 80 pF
Coarse
1
Fine
After reset, the unity gain buffer is engaged. With a
2.5V reference this would make the full scale input
range default to 2.5 V. By activating the instrumen-
tation amplifier (i.e. a gain setting other than 1) and
using a gain setting of 32, the full scale input range
can quickly be set to 2.5/32 or about 78 mV. Note
that these input ranges assume the calibration regis-
ters are set to their default values (i.e. Gain = 1.0 and
Offset = 0.0).
2.1.2. Multiplexed Settling Limitations
The settling performance of the CS5531/32/33/34
in multiplexed applications is affected by the sin-
gle-pole low-pass filter which follows the instru-
mentation amplifier (see Figure 3). To achieve data
sheet settling and linearity specifications, it is rec-
ommended that a 22 nF C0G capacitor be used. Ca-
pacitors as low as 10 nF or X7R type capacitors can
also be used with some minor increase in distortion
for AC signals.
2.1.3. Voltage Noise Density Performance
Figure 5 illustrates the measured voltage noise den-
sity versus frequency from 0.01 Hz to 10 Hz of a
CS5532-BS. The device was powered with ±2.5 V
supplies, using 120 Sps OWR, the 64x gain range,
bipolar mode, and with the input short bit enabled.
2.1.4. No Offset DAC
An offset DAC was not included in the CS553X
family because the high dynamic range of the con-
verter eliminates the need for one. The offset regis-
Figure 5. Measured Voltage Noise Density
100
10
1
0.01
0.1
Frequency (Hz)
CS5531/32/33/34
1
Gain = 64
10
15