DC1540A Linear Technology, DC1540A Datasheet - Page 43

• Manufacturer Part Number: DC1540A
• Description: LTC2978 Demoboard (includes DC1360A + DC1361A), Requires DC1613A
• Manufacturer: Linear Technology
• Series: -r

Specifications of DC1540A

• Design Resources: DC1540 Design File
• Main Purpose: Power Management, Power Supply Supervisor/Tracker/Sequencer
• Embedded: No
• Utilized Ic / Part: LTC2978
• Primary Attributes: Voltage Detector & Supervisor
• Secondary Attributes: -
• Kit Application Type: Power Management
• Application Sub Type: Power Supply Controller
• Features: Demonstration System For The LTC2978 Octal I2C / SMBus / PMBus Power Supply Monitor & Controller
• Lead Free Status / Rohs Status: Not applicable / Not applicable

of this register are reset to ‘h7C00 when the LTC2978
emerges from power-on reset or when a CLEAR_FAULTS
command is executed.
MFR_TEMPERATURE_PEAK Data Contents
MFR_DAC
This command register returns the 10-bit value for the
voltage-buffered current DAC. This register may be writ-
ten when Mfr_config_dac_mode is configured for either
of the two manual DAC modes.
MFR_DAC Data Contents
MFR_POWERGOOD_ASSERTION_DELAY
This command register allows the user to program the
delay from when the internal power good signal becomes
valid until the power good output is asserted.
MFR_POWERGOOD_ASSERTION_DELAY Data Contents
operaTion
b[15:0] Mfr_powergood_assertion_delay The data uses the linear format:
b[15:0] Mfr_temperature_peak[15:0] The data uses the linear format:
b[15:10] Reserved
BIT(S) SYMBOL
BIT(S) SYMBOL
BIT(S) SYMBOL
b[9:0]
Mfr_dac_direct_val Voltage-buffered current DAC code value.
OPERATION
Read only, always returns ‘h3F .
OPERATION
V(Symbol) = Y • 2
Where N = b[15:11] is a 5-bit
two’s complement integer and
Y = b[10:0] is an 11-bit two’s
complement integer
Units: °C.
OPERATION
T(Symbol) = Y • 2
Where N = b[15:11] is a 5-bit
two’s complement integer and
Y = b[10:0] is an 11-bit two’s
complement integer.
This delay is counted using
internal clock independent of
SHARE_CLK.
Delays are rounded to the
nearest 200µs
Units: ms. Max delay is 13.1
sec.
N
N
MFR_WATCHDOG_T_FIRST and MFR_WATCHDOG_T
The MFR_WATCHDOG_T_FIRST register allows the user to
program the duration of the first watchdog timer interval
following assertion of the POWER GOOD signal, assuming
the POWER GOOD signal reflects the status of the watchdog
timer. If assertion of POWER GOOD is not conditioned by the
watchdog timer’s status, then MFR_WATCHDOG_T_FIRST
applies to the first timing interval after the timer is enabled.
Writing a value of 0ms to the MFR_WATCHDOG_T_FIRST
register disables the watchdog timer.
The MFR_WATCHDOG_T register allows the user to
program watchdog time intervals subsequent to the
MFR_WATCHDOG_T_FIRST timing interval. Writing a
value of 0ms to the MFR_WATCHDOG_T register disables
the watchdog timer. A non-zero write to MFR_WATCH-
DOG_T will reset the watchdog timer.
MFR_WATCHDOG_T_POR and MFR_WATCHDOG_T Data
Contents
b[15:0] Mfr_watchdog_t_first
BIT(S) SYMBOL
Mfr_watchdog_t
OPERATION
The data uses the linear format:
T(Symbol) = Y • 2
Where N = b[15:11] is a 5-bit two’s
complement integer and
Y = b[10:0] is an 11-bit two’s
complement integer
These timers operate on an internal
clock independent of SHARE_CLK.
Delays are rounded to the nearest 10µs
for _t and 1ms for _t_first.
Writing a zero value for Y to the
Mfr_watchdog_t or Mfr_watchdog_t_
first registers will disable the watchdog
timer.
Units: ms. Max timeout is 0.6 sec for _t
and 65 sec for _t_first
LTC2978
N

2978fa