DC1540A Linear Technology, DC1540A Datasheet - Page 44

• Manufacturer Part Number: DC1540A
• Description: LTC2978 Demoboard (includes DC1360A + DC1361A), Requires DC1613A
• Manufacturer: Linear Technology
• Series: -r

Specifications of DC1540A

• Design Resources: DC1540 Design File
• Main Purpose: Power Management, Power Supply Supervisor/Tracker/Sequencer
• Embedded: No
• Utilized Ic / Part: LTC2978
• Primary Attributes: Voltage Detector & Supervisor
• Secondary Attributes: -
• Kit Application Type: Power Management
• Application Sub Type: Power Supply Controller
• Features: Demonstration System For The LTC2978 Octal I2C / SMBus / PMBus Power Supply Monitor & Controller
• Lead Free Status / Rohs Status: Not applicable / Not applicable

MFR_PAGE_FF_MASK
The MFR_PAGE_FF_MASK command is used to select
which channels respond when the global page (FF) is in
use. Note that the only commands that support PAGE =
‘hFF are OPERATION and ON_OFF_CONFIG.
MFR_PAGE_FF_MASK Data Contents
MFR_PADS
The MFR_PADS command provides read only access to
slow frequency digital pads. The input values presented
in bits[9:0] are before any deglitching logic.
MFR_PADS_PWRGD_DRIVE Data Contents
LTC2978
operaTion

BIT(S) SYMBOL
b[13:10] Mfr_pads_faultb_drive[3.0] Bit[3] used for FAULTB00 pad,
b[7:0] Mfr_page_ff_mask Global page response enable, per channel
BIT(S) SYMBOL
b[9:8]
b[7:6]
b[15]
b[14]
Mfr_pads_pwrgd_drive
Mfr_pads_alertb_drive
Mfr_pads_asel1[1:0]
Mfr_pads_asel0[1:0]
OPERATION
Each bit enables/disables the
corresponding channel:
0 = ignore global page accesses
1 = fully respond to global page accesses
OPERATION
0 = PWRGD pad is being driven
low by this chip
1 = PWRGD pad is not being
driven low by this chip
0 = ALERTB pad is being driven
low by this chip
1 = ALERTB pad is not being
driven low by this chip
bit[2] used for FAULTB01 pad,
bit[1] used for FAULTB10 pad,
bit[0] used for FAULTB11 pad
as follows:
0 = FAULTB pad is being driven
low by this chip
1 = FAULTB pad is not being
driven low by this chip
11: Logic high detected on ASEL1
input pad
10: ASEL1 input pad is floating
01: Reserved
00: Logic low detected on ASEL1
input pad
11: Logic high detected on ASEL0
input pad
10: ASEL0 input pad is floating
01: Reserved
00: Logic low detected on ASEL0
input pad
MFR_I2C_BASE_ADDRESS
The MFR_I2C_BASE_ADDRESS command determines the
base value for the I
MFR_I2C_BASE_ADDRESS Data Contents
MFR_SPECIAL_ID
This register contains the manufacturer ID for the
LTC2978.
MFR_SPECIAL_ID Data Contents
MFR_SPECIAL_LOT
These paged registers contain information that identifies the
user configuration that was programmed at the factory.
MFR_SPECIAL_LOT Data Contents
BIT(S) SYMBOL
BIT(S)
b[15:0]
BIT(S)
b[7:0]
b[6:0] i2c_base_address
b[7]
b[3:0]
b[5]
b[4]
Reserved
Mfr_pads_control1
Mfr_pads_control0
Mfr_pads_faultb[3:0]
SYMBOL
Mfr_special_id
SYMBOL
Mfr_special_lot
2
C address byte.
OPERATION
Read only, always returns 0.
This 7-bit value determines the base value
of the 7-bit I
OPERATION
Read only, always returns ‘h0121
OPERATION
Contains the LTC default special lot
number. Contact the factory to request
a custom factory programmed user
configuration and special lot number.
1: Logic high detected on
CONTROL1 pad
0: Logic low detected on
CONTROL1 pad
1: Logic high detected on
CONTROL0 pad
0: Logic low detected on
CONTROL0 pad
Bit[3] used for FAULTB00 pad,
bit[2] used for FAULTB01 pad,
bit[1] used for FAULTB10 pad,
bit[0] used for FAULTB11 pad
as follows:
1: Logic high detected on
FAULTBzn pad
0: Logic low detected on
FAULTBzn pad
2
C address.
2978fa