NCT6627UD Nuvoton Technology Corporation of America, NCT6627UD Datasheet - Page 117

• Manufacturer Part Number: NCT6627UD
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of NCT6627UD

• Lead Free Status / Rohs Status: Supplier Unconfirmed

The Data Rate Register is used to set the transfer rate and write precompensation. However, in PC-AT and PS/2
Model 30 and PS/2 modes, the data rate is controlled by the CC register, not by the DR register. As a result, the
real data rate is determined by the most recent write to either the DR or CC register. The bit definitions for this
register are as follows:
DEFAULT
9.2.6 Data Rate Register (DR Register) (Write base address + 4)
NAME
BIT
BIT
5
4
3
2
1
0
BIT
7
6
5
4
3
2
1
Non-DMA mode. The FDC is in the non-DMA mode, this bit is set only during the
execution phase in non-DMA mode.
FDC Busy (CB). A read or write command is in the process when CB = HIGH.
FDD 3 Busy. (D3B = 1) FDD number 3 is in the SEEK mode.
FDD 2 Busy. (D2B = 1) FDD number 2 is in the SEEK mode.
FDD 1 Busy. (D1B = 1) FDD number 1 is in the SEEK mode.
FDD 0 Busy. (D0B = 1) FDD number 0 is in the SEEK mode.
S/W RESET. The software reset bit.
POWER DOWN.
0: FDC in normal mode.
1: FDC in power-down mode.
0
PRECOMP 2.
PRECOMP 1.
PRECOMP 0.
DRATE 1.
RESET
S/W
7
0
POWER
DOWN
6
0
5
0
PRECOMP2
DESCRIPTION
DESCRIPTION
4
0
PRECOMP1
Selects the value of write precompensation.
The
precompensation
combination of these bits. Please see the
tables below.
Select the data rate of the FDC and
reduced write-current control.
Bits
1 0
0 0: 500 KB/S (MFM), 250 KB/S (FM),
RWC# = 1
-108-
3
0
W83627UHG/NCT6627UD
following
PRECOMP0
Publication Release Date: October 26, 2010
2
0
tables
values
DRATE1
1
1
show
for
DRATE0
every
0
0
the
Revision 1.7