NCT6627UD Nuvoton Technology Corporation of America, NCT6627UD Datasheet - Page 126

• Manufacturer Part Number: NCT6627UD
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of NCT6627UD

• Lead Free Status / Rohs Status: Supplier Unconfirmed

BDLAB = 0
BDLAB = 0
BDLAB = 0
BDLAB = 1
BDLAB = 1
Register Address Base
+ 0
+ 0
+ 1
+ 2
+ 2
+ 3
+ 4
+ 5
+ 6
+ 7
+ 0
+ 1
*: Bit 0 is the least significant bit. The least significant bit is the first bit serially transmitted or received.
**: These bits are always 0 in 16450 Mode.
Interrupt Control
Interrupt Status
Status Register
Buffer Register
UART Control
UART Status
User Defined
Divisor Latch
Divisor Latch
(Read Only)
(Write Only)
(Read Only)
(Write Only)
UART FIFO
Transmitter
Handshake
Handshake
Baudrate
Receiver
Register
Register
Register
Register
Register
Register
Register
Register
Baudrate
Control
Control
Buffer
High
Low
UCR
HCR
UDR
RBR
TBR
UFR
USR
HSR
BHL
ICR
ISR
BLL
RBR Data
RBR Data
RX Data
TX Data
Terminal
Toggling
Interrupt
(ERDRI)
Interrupt
Pending
(DLS0)
(TCTS)
Enable
Enable
Length
Ready
Ready
Ready
Select
(DTR)
(RDR)
FIFO
Data
Data
Bit 0
Bit 0
“0” if
Bit 0
CTS
Bit 0
Bit 0
Bit 8
0
(ETBREI)
RX Data
Toggling
TX Data
Interrupt
Interrupt
Request
Table 10-1 Register Summary for UART
Overrun
(TDSR)
Enable
Length
(DLS1)
Empty
Status
RCVR
Select
(OER)
Bit (0)
Reset
(RTS)
FIFO
Send
Error
Data
DSR
Bit 1
Bit 1
TBR
Bit 1
Bit 1
Bit 1
Bit 9
to
1
Loopback
RI Falling
Stop Bits
Parity Bit
RX Data
TX Data
(EUSRI)
Interrupt
(MSBE)
Interrupt
Multiple
(PBER)
Enable
Enable
(FERI)
Status
Bit (1)
Reset
Bit 10
XMIT
FIFO
Input
Edge
Error
Bit 2
Bit 2
Bit 2
Bit 2
USR
RI
2
Bit Number
RX Data
Interrupt
(EHSRI)
Interrupt
Toggling
TX Data
No Stop
Bit (2)**
(NSER)
(TDCD)
Enable
Enable
Enable
Status
Select
Parity
(PBE)
Bit 11
Mode
HSR
DMA
Error
DCD
Bit 3
Bit 3
Bit 3
Bit 3
IRQ
Bit
Bit
-117-
3
W83627UHG/NCT6627UD
Loopback
Reserved
Detected
RX Data
TX Data
to Send
Internal
Enable
Enable
(SBD)
Parity
(EPE)
(CTS)
Silent
Bit 12
Even
Clear
Bit 4
Bit 4
Byte
Bit 4
Bit 4
4
0
0
Publication Release Date: October 26, 2010
Reversed
RX Data
TX Data
Bit Fixed
Data Set
(TBRE)
Enable
PBFE)
Empty
Ready
(DSR)
Parity
Bit 13
Bit 5
Bit 5
TBR
Bit 5
Bit 5
5
0
0
0
Active Level
RX Data
Interrupt
Indicator
TX Data
Enabled
Silence
(TSRE)
Enable
FIFOs
Empty
(SSE)
(LSB)
Bit 14
Bit 6
Bit 6
TSR
Ring
Bit 6
Bit 6
(RI)
Set
RX
**
6
0
0
Active Level
Data Carrier
Revision 1.7
Access Bit
Indication
RX Data
Baudrate
(BDLAB)
RX FIFO
(RFEI) **
TX Data
Enabled
Interrupt
Divisor
FIFOs
(MSB)
Detect
(DCD)
Latch
Bit 15
Error
Bit 7
Bit 7
Bit 7
Bit 7
RX
**
7
0
0