DS3154+ Maxim Integrated Products, DS3154+ Datasheet

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GENERAL DESCRIPTION The DS3151 (single), DS3152 (dual), DS3153 (triple), and DS3154 (quad) line interface units (LIUs) perform the functions necessary for interfacing at the physical layer to DS3, E3, or STS-1 lines. Each LIU has independent receive and transmit ...

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DETAILED DESCRIPTION.................................................................................................5 2. APPLICATIONS .................................................................................................................7 3. HARDWARE MODE AND CPU BUS MODE......................................................................8 4. PIN DESCRIPTIONS ........................................................................................................10 5. REGISTER DESCRIPTIONS ............................................................................................15 6. RECEIVER........................................................................................................................22 7. TRANSMITTER ................................................................................................................25 8. DIAGNOSTICS .................................................................................................................28 9. JITTER ATTENUATOR ....................................................................................................29 10. RESET LOGIC..................................................................................................................30 11. TRANSFORMERS............................................................................................................31 12. JTAG ...

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Figure 1-1. External Connections ...............................................................................................................7 Figure 2-1. 4-Port Unchannelized DS3/E3 Card.........................................................................................7 Figure 3-1. Hardware Mode Block Diagram ...............................................................................................8 Figure 3-2. CPU Bus Mode Block Diagram ................................................................................................9 Figure 5-1. Status Register Logic .............................................................................................................16 Figure 6-1. Receiver Jitter Tolerance .......................................................................................................24 Figure 7-1. ...

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Table 1-A. Applicable Telecommunications Standards ..............................................................................6 Table 4-A. Active I/O Pins—Hardware and CPU Bus Modes...................................................................10 Table 4-B. Transmitter Pin Descriptions ...................................................................................................11 Table 4-C. Receiver Pin Descriptions.......................................................................................................12 Table 4-D. Global Pin Descriptions ..........................................................................................................13 Table 4-E. JTAG and Test Pin Descriptions .............................................................................................14 ...

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FEATURES (continued) Receiver AGC/equalizer block handles from 0 to 15dB of cable loss Loss-of-lock (LOL) PLL status indication Interfaces directly to a DSX monitor signal (~20dB flat loss) using built-in preamp Digital and analog loss-of-signal (LOS) detectors (ANSI T1.231 and ...

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Table 1-A. Applicable Telecommunications Standards SPECIFICATION T1.102-1993 Digital Hierarchy—Electrical Interfaces T1.107-1995 Digital Hierarchy—Formats Specification T1.231-1997 Digital Hierarchy—Layer 1 In-Service Digital Transmission Performance Monitoring T1.404-1994 Network-to-Customer Installation—DS3 Metallic Interface Specification G.703 Physical/Electrical Characteristics of Hierarchical Digital Interfaces, 1991 Digital Multiplex Equipment ...

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Figure 1-1. External Connections TRANSMIT 1:2ct RECEIVE 1:2ct 2. APPLICATIONS Figure 2-1. 4-Port Unchannelized DS3/E3 Card Shorthand Notations. The notation “DS315x” throughout this data sheet refers to either the DS3151, DS3152, DS3153, or DS3154. This data sheet is the specification ...

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HARDWARE MODE AND CPU BUS MODE The DS315x can operate in either hardware mode or CPU bus mode. In hardware mode, pulling configuration input pins high or low does all configuration, and all status information is reported on status ...

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Figure 3-2. CPU Bus Mode Block Diagram T3MCLK E3MCLK V DD Power Clock Mux Supply V SS Automatic Gain RXPn Control + Adaptive Equalizer RXNn ALOS Analog Local Loopback TDMn Driver Monitor TXPn TXNn Loopback Control TTSn DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 ...

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PIN DESCRIPTIONS Table 4-A. Active I/O Pins—Hardware and CPU Bus Modes NAME TYPE TCLKn I TPOSn/TDATn I TNEGn I TXPn, TXNn O TTSn I TDMn O TDSAn, TDSBn I TLBOn I TJAn I RXPn, RXNn I RCLKn O RPOSn/RDATn ...

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Table 4-B. Transmitter Pin Descriptions NAME I/O Transmitter Clock. A DS3 (44.736MHz ±20ppm), E3 (34.368MHz ±20ppm), or STS-1 (51.840MHz ±20ppm) clock should be applied at this signal. Data to be transmitted is clocked into the device at TCLKn I TPOS/TDAT ...

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Table 4-C. Receiver Pin Descriptions NAME I/O RXPn, Receiver Analog Inputs. These differential AMI inputs are coupled to the inbound 75Ω coaxial cable I RXNn through a 1:2 step-up transformer Receiver Clock. The recovered clock is output on the RCLK ...

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Table 4-D. Global Pin Descriptions NAME I/O High-Z Enable Input (Active Low, Open Drain) HIZ 0 = tri-state all output pins (Note that the JTRST pin must be low normal operation Reset Input (Active Low, Open ...

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NAME I/O transaction, with R indicating a read and R indicating a write. Read Enable (Active Low) or Data Strobe (Active Low). In Intel bus mode (MOT = 0 asserted RD/DS to read internal ...

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REGISTER DESCRIPTIONS When the DS315x is configured in CPU bus mode (HW = 0), the registers shown in through the CPU bus interface. All registers for the LIU ports are forced to their default values during an internal power-on ...

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Status Register Description The status registers have two types of status bits. Real-time status bits—located in the SRn registers—indicate the state of a signal at the time it was read. Latched status bits—located in the SRLn registers—are set when a ...

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Register Name: Register Description: Register Address: Bit 7 6 Name — TBIN Default 0 0 Bit 6: Transmitter Binary Interface Enable (TBIN Transmitter framer interface is bipolar on the TPOS and TNEG pins. The B3ZS/HDB3 encoder is disabled. ...

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Register Name: Register Description: Register Address: Bit 7 6 Name ITU RBIN Default 0 0 Bit 7: ITU CV Mode (ITU). This bit controls what types of bipolar violations (BPVs) are flagged as code violations on the RLCV pin and ...

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Register Name: Register Description: Register Address: Bit 7 6 Name — — Default — — Bit 5: Transmitter Driver Monitor (TDM). This read-only status bit indicates the current state of the transmit driver monitor the transmitter is operating ...

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Register Name: Register Description: Register Address: Bit 7 6 Name — — Default — — Bit 5: Transmitter Driver Monitor Latched (TDML). This latched status bit is set to one when the TDM status bit changes state (low to high ...

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Register Name: Register Description: Register Address: Bit 7 6 Name — — Default — — Bit 5: Transmitter Driver Monitor Interrupt Enable (TDMIE mask TDML interrupt 1 = enable TDML interrupt Bit 4: PRBS Detector Interrupt Enable (PRBSIE) ...

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RECEIVER Interfacing to the Line. The receiver can be transformer-coupled or capacitor-coupled to the line. Typically, the receiver interfaces to the incoming coaxial cable (75Ω) through a 1:2 step-up transformer. arrangement of the transformer and other recommended interface components. ...

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For E3 RLOS Assertion: 1) The ALOS detector in the AGC/equalizer block detects that the incoming signal is less than or equal to a signal level approximately 24dB below nominal, and mutes the data coming out of the clock and ...

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ITU bit set to 1 – A BPV with the same polarity as the last BPV. When RLCV is asserted to flag a BPV, the RDAT pin outputs a one. The state bit that tracks the polarity of the last ...

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TRANSMITTER Transmit Clock. The clock applied at the TCLK input clocks in data on the TPOS/TDAT and TNEG pins. If the jitter attenuator is not enabled in the transmit path, the signal on TCLK is the transmit line clock ...

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Transmitter Power-Down. To minimize power consumption when the transmitter is not being used, assert the TPD configuration bit (CPU bus mode only). When the transmitter is powered down, the TXP and TXN pins are put in a high-impedance state and ...

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Table 7-D. STS-1 Waveform Test Parameters and Limits PARAMETER Rate Line Code Transmission Medium Test Measurement Point Test Termination Pulse Amplitude Pulse Shape Unframed All-Ones Power Level at 25.92MHz Unframed All-Ones Power Level at 51.84MHz Table 7-E. E3 Waveform Test ...

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Figure 7-2. DS3 AIS Structure M1 Subframe Info F1 Info C1 (1) Bits (1) Bits (0) M2 Subframe Info F1 Info C1 (1) Bits (1) Bits (0) M3 Subframe Info F1 ...

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Loopbacks. Each LIU has three internal loopbacks. See (hardware mode) or LLB and RLB control bits (CPU bus mode) enable these loopbacks. When LLB = RLB = 0, loopbacks are disabled. Setting RLB = 1 with LLB = 0 enables ...

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JA must take its master clock from the MCLK pin. The clock and data recovery block also uses the selected master clock. The JA has a loop bandwidth of master_clock / 2,058,874 (see corner frequencies in attenuates jitter at ...

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TRANSFORMERS Table 11-A. Transformer Characteristics PARAMETER Turns Ratio 0.250MHz to 500MHz (typ) Bandwidth 75Ω Primary Inductance Leakage Inductance Interwinding Capacitance Isolation Voltage Table 11-B. Recommended Transformers NO. OF MANUFACTURER TRANSFORMERS 1 Pulse Engineering Halo Electronics 1 ...

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JTAG TEST ACCESS PORT AND BOUNDARY SCAN 12.1 JTAG Description The DS315x LIUs support the standard instruction codes SAMPLE/PRELOAD, BYPASS, and EXTEST. Optional public instructions included are HIGHZ, CLAMP, and IDCODE. contain the following items, which meet the requirements ...

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JTAG TAP Controller State Machine Description This section discusses the operation of the TAP controller state machine. The TAP controller is a finite state machine that responds to the logic level at JTMS on the rising edge of JTCLK. ...

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Shift-DR. The test data register selected by the current instruction is connected between JTDI and JTDO and shifts data one stage toward its serial output on each rising edge of JTCLK test register selected by the current instruction ...

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JTAG Instruction Register and Instructions The instruction register contains a shift register as well as a latched parallel output and is 3 bits in length. When the TAP controller enters the Shift-IR state, the instruction shift register is connected ...

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JTAG Test Registers IEEE 1149.1 requires a minimum of two test registers—the bypass register and the boundary scan register. An optional test register, the identification register, has been included in the device design used with the IDCODE ...

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ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Lead with Respect to V Supply Voltage Range (V ) with Respect Ambient Operating Temperature Range Junction Operating Temperature Range Storage Temperature Range Soldering Temperature Stresses beyond ...

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Table 13-C. Framer Interface Timing = 3.3V ±5 -40°C to +85°C PARAMETER RCLK/TCLK Clock Period RCLK Duty Cycle TCLK Duty Cycle MCLK Duty Cycle TPOS/TDAT, TNEG to TCLK Setup Time TPOS/TDAT, TNEG Hold Time RCLK ...

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Figure 13-2. Receiver Framer Interface Timing Diagram RCLK (NORMAL) RCLK (INVERTED) t7 RPOS/RDAT, RNEG/RLCV Table 13-D. Receiver Input Characteristics—DS3 and STS-1 Modes = 3.3V ±5 -40°C to +85°C PARAMETER Receive Sensitivity (Length of Cable) Signal-to-Noise ...

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Table 13-F. Transmitter Output Characteristics—DS3 and STS-1 Modes = 3.3V ±5 -40°C to +85°C DS3 Output Pulse Amplitude, TLBO = 0 (Note 17) DS3 Output Pulse Amplitude, TLBO = 1 (Note 17) STS-1 Output Pulse ...

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Figure 13-3. CPU Bus Timing Diagram (Nonmultiplexed) INTEL READ CYCLE A[5:0] D[7: INTEL WRITE CYCLE A[5:0] ADDRESS VALID D[7: DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs ADDRESS VALID DATA VALID ...

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Figure 13-3. CPU Bus Timing Diagram (Nonmultiplexed)(continued) MOTOROLA READ CYCLE A[5:0] D[7:0] R MOTOROLA WRITE CYCLE A[5:0] D[7:0] R DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs ADDRESS VALID DATA VALID t2 t3 ADDRESS VALID ...

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Figure 13-4. CPU Bus Timing Diagram (Multiplexed) INTEL READ CYCLE t13 ALE t11 ADDRESS A[5:0] VALID t14 D[7:0] t14 NOTE: t14 STARTS ON THE OCCURRENCE OF EITHER THE RISING EDGE OF ALE OR A VALID ADDRESS, WHICHEVER ...

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Figure 13-4. CPU Bus Timing Diagram (Multiplexed) (continued) MOTOROLA READ CYCLE t13 ALE t11 ADDRESS A[5:0] VALID t14 D[7:0] t14 R NOTE: t14 STARTS ON THE OCCURRENCE OF EITHER THE RISING EDGE OF ALE OR A VALID ADDRESS, ...

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Table 13-I. JTAG Interface Timing = 3.3V ±5 -40°C to +85°C PARAMETER JTCLK Clock Period JTCLK Clock High/Low Time (Note 23) JTCLK to JTDI, JTMS Setup Time JTCLK to JTDI, JTMS Hold Time JTCLK to ...

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PIN ASSIGNMENTS Table 14-A lists pin assignments sorted by signal name. DS3154 has all four LIUs. DS3153 has only LIUs 1, 2, and 3. DS3152 has only LIUs 1 and 2. DS3151 has only LIU 1. Figure 14-1 through ...

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HARDWARE NAME MODE MODE RNEGn Y RPOSn Y RST Y RTSn Y RXNn Y RXPn Y STMCLK Y STSn Y T3MCLK Y TBIN Y TCINV Y TCLKn Y TDMn Y TDSAn Y TDSBn Y TEST Y TJAn Y TLBOn Y ...

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Table 14-B. Pin Assignments Sorted by Pin Number DS3154 PIN HARDWARE CPU BUS MODE MODE RLOS1 RLOS1 A1 A2 RXN1 RXN1 A3 RXP1 RXP1 A4 RMON1 N.C. A5 T3MCLK T3MCLK A6 TXN3 TXN3 A7 TXP3 TXP3 A8 TCLK3 TCLK3 A9 ...

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DS3154 PIN HARDWARE CPU BUS MODE MODE E10 RLB3 N.C. E11 LLB3 N.C. E12 E3MCLK E3MCLK F1 TXP1 TXP1 F2 STS1 D1 F3 E3M1 ...

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DS3154 PIN HARDWARE CPU BUS MODE MODE K9 TJA2 N.C. K10 RNEG2 RNEG2 K11 RPOS2 RPOS2 K12 RCLK2 RCLK2 L1 RXN4 RXN4 RTS4 RTS4 L2 L3 RPOS4 RPOS4 L4 TNEG4 TNEG4 TTS4 TTS4 L5 L6 STS4 A1 L7 TDSA4 A3 ...

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Figure 14-1. DS3151 Hardware Mode Pin Assignment RLOS1 RXN1 RXP1 RMON1 RTS1 PRBS1 N.C. RJA1 RCLK1 RPOS1 RNEG1 TJA1 TDM1 JTRST TPOS1 TNEG1 E1 ...

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Figure 14-2. DS3151 CPU Bus Mode Pin Assignment RLOS1 RXN1 RXP1 N. RTS1 PRBS1 N.C. N. RCLK1 RPOS1 RNEG1 N. TDM1 JTRST TPOS1 TNEG1 ...

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Figure 14-3. DS3152 Hardware Mode Pin Assignment RLOS1 RXN1 RXP1 RMON1 RTS1 PRBS1 N.C. RJA1 RCLK1 RPOS1 RNEG1 TJA1 TDM1 JTRST TPOS1 TNEG1 E1 ...

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Figure 14-4. DS3152 CPU Bus Mode Pin Assignment RLOS1 RXN1 RXP1 N. RTS1 PRBS1 N.C. N. RCLK1 RPOS1 RNEG1 N. TDM1 JTRST TPOS1 TNEG1 TTS1 ...

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Figure 14-5. DS3153 Hardware Mode Pin Assignment RLOS1 RXN1 RXP1 RMON1 RTS1 PRBS1 N.C. RJA1 RCLK1 RPOS1 RNEG1 TJA1 TDM1 JTRST TPOS1 TNEG1 E1 ...

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Figure 14-6. DS3153 CPU Bus Mode Pin Assignment RLOS1 RXN1 RXP1 N. RTS1 PRBS1 N.C. N. RCLK1 RPOS1 RNEG1 N. TDM1 JTRST TPOS1 TNEG1 ...

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Figure 14-7. DS3154 Hardware Mode Pin Assignment RLOS1 RXN1 RXP1 RMON1 RTS1 PRBS1 N.C. RJA1 RCLK1 RPOS1 RNEG1 TJA1 TDM1 JTRST TPOS1 TNEG1 E1 ...

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Figure 14-8. DS3154 CPU Bus Mode Pin Assignment RLOS1 RXN1 RXP1 N. RTS1 PRBS1 N.C. N. RCLK1 RPOS1 RNEG1 N. TDM1 JTRST TPOS1 TNEG1 ...

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PACKAGE INFORMATION (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information www.maxim-ic.com/DallasPackInfo.) Note: All dimensions in millimeters 1.00 (1.00) (1.00) BOTTOM VIEW ...

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THERMAL INFORMATION Table 16-A. Thermal Properties, Natural Convection PARAMETER Ambient Temperature (Note 1) Junction Temperature Theta-JA (θ ), Still Air (Note 2) JA Psi-JB Psi-JT Note 1: The package is mounted on a four-layer JEDEC standard test board with ...

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... No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor Corporation. DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs DESCRIPTION : -10μ ...