ST7538P013TR STMicroelectronics, ST7538P013TR Datasheet - Page 12

• Manufacturer Part Number: ST7538P013TR
• Description: IC TXRX FSK POWER LINE 44TQFP
• Manufacturer: STMicroelectronics
• Type: Transceiverr

Specifications of ST7538P013TR

• Number Of Drivers/receivers: 1/1
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Package / Case: 44-TQFP Exposed Pad, 44-eTQFP, 44-HTQFP, 44-VQFP
• For Use With: 497-5484 - BOARD EVAL ST7538 PWR LINE TXRX
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Protocol: -
• Other names: 497-4316-2

ST7538
– Synchronous mode.
ST7538 allows to interface the host Controller using a four lines synchronous interface (RXD,TXD, CLR/
T &
). ST7538 is always the master of the communication and provides the clock reference on CLR/
RxTx
T line.
When ST7538 is in receiving mode an internal PLL recovers the clock reference. Data on RxD line are
stable on CLR/T rising Edge.
When ST7538 is in transmitting mode the clock reference is internally generated and data are read on TxD
line on CLR/T rising Edge.
If
line is set to “1” & REG_DATA=”0” (Data Reception), ST7538 enters in an Idle State and CLR/T
RxTx
line is forced Low. After Tcc time the modem starts providing received data on RxD line.
If
line is set to “0” & REG_DATA=”0” (Data Transmission), ST7538 enters in an Idle State and trans-
RxTx
mission circuitry is switched on. After Tcc time the modem starts transmitting data present on TXD line
(figure 6) .
Figure 5. Receiving and transmitting data/recovered clock timing
Receiving Bit Synchronization
Transmitting Bit Synchronization
CLR/T
CLR/T
RxD
TxD
T
T
S
H
D03IN1416
Figure 6. Data Reception -> Data Transmission -> Data reception
T
T
CC
CC
CLR_T
T
T
T
B
DS
DH
RXD
REG_DATA
T
T
CR
CR
RxTx
T
T
S
H
BIT23
BIT22
TXD
D03IN1402
3.5 Control Register Access
The communication with ST7538 Control Register is always synchronous. The access is achieved using
the same lines of the Mains interface (RxD, TxD and CLR/T) plus REG_DATA Line.
With REG_DATA = 1 and
=0, the data present on TxD are loaded into the Control Register MSB first.
RxTx
The ST7538 samples the TxD line on CLR/T rising edges. The control Register content is updated at the
end of the register access section (REG_DATA falling edge). If more than 24 bits are transferred to
ST7538 only the latest 24 bits are stored inside the Control Register.
With REG_DATA = 1 and
=1, the content of the Control Register is sent on RxD port. The Data on
RxTx
RxD are stable on CLR/T rising edges MSB First.
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