CY7C68000A-56LFXC Cypress Semiconductor Corp, CY7C68000A-56LFXC Datasheet
CY7C68000A-56LFXC
Specifications of CY7C68000A-56LFXC
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CY7C68000A-56LFXC Summary of contents
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... UTMI bus, while suspended, to enable the bus to be shared with other devices. Two packages are defined for the families: 56-pin QFN and 56-pin VFBGA. The functional block diagram follows. • 198 Champion Court • San Jose CY7C68000A Tri_state , CA 95134-1709 • 408-943-2600 Revised May 22, 2009 [+] Feedback ...
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... HS Idle state on the bus. The XcvrSelect signal is the control that selects either the FS trans- ceivers or the HS transceivers. By setting this pin to a ‘0’ the HS transceivers are selected and by setting this bit to a’1’ the FS transceivers are selected. CY7C68000A has reached 3.3V. CC Page [+] Feedback ...
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... DPLUS/DMINUS lines and ‘0’s become ‘K’s. DPLUS/DMINUS Impedance Termination The CY7C68000A does not require external resistors for USB data line impedance termination or an external pull up resistor on the DPLUS line. These resistors are incorporated into the part. ...
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... Pin Configurations The following pages illustrate the individual pin diagrams that are available in the 56-pin QFN and 56-pin VFBGA packages. The packages offered use either an 8-bit (60 MHz) or 16-bit (30 MHz) bus interface. Figure 1. CY7C68000A 56-pin QFN Pin Assignment TXReady 1 Suspend 2 Reset 3 AV ...
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... Figure 2. CY7C68000A 56-pin VFBGA Pin Assignment Document #: 38-08052 Rev CY7C68000A Page [+] Feedback ...
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... HS termination 1: FS termination N/A Suspend Places the CY7C68000A in a mode that draws minimal power from supplies. Shuts down all blocks not necessary for Suspend/Resume operations. While suspended, TermSelect must always mode to ensure that the 1.5 Kohm pull up on DPLUS remains powered. ...
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... TX Holding Register on the rising edge of CLK. If TXValid is TRUE and TXReady is asserted at the rising edge of CLK, the CY7C68000A loads the data on the data bus into the TX Holding Register on the next rising edge of CLK. At that time, the SIE ...
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... CC N Connect to 3.3V power source Connect to 3.3V power source Connect to 3.3V power source. CC N/A Ground. N/A Ground. N/A Ground. N/A Ground. N/A Ground. Connect pin to Ground. Connect pin to Ground. Connect pin to Ground. Connect pin to Ground. CY7C68000A [1] (continued) Page [+] Feedback ...
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... Crystal Frequency) ... 24 MHz ± 100 ppm OSC ................................................................... Parallel Resonant Conditions 0< V < OUT I = –4 mA OUT Except DPLUS/DMINUS/CLK DPLUS/DMINUS/CLK Output pins [2] Connected [2] Disconnected Normal operation OPMOD[1: Normal operation OPMOD[1: CY7C68000A Min Typ Max Unit 3.0 3.3 3 5.25 V –0.5 0.8 V μA ±10 2 ...
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... Minimum hold time for Data (transmit direction) DH_MIN T Clock to Control out time for TXReady, RXValid, CCO RXActive and RXError T Clock to Data out time (Receive direction) CDO Document #: 38-08052 Rev. *H Figure 3. 60 MHz Interface Timing Constraints TCH_MIN TDH_MIN TCCO TCDO Min CY7C68000A Typ Max Unit Notes Page [+] Feedback ...
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... Minimum setup time for Tristate tssu T Propagation Delay for Tristate mode tspd Document #: 38-08052 Rev. *H TCH_MIN TDH_MIN TCDO TCCO TCVO TVH_MIN Min Figure 5. Tristate Mode Timing Constraints Ttssu Ttspd XXXX Hi-Z Min 0 CY7C68000A Typ Max Unit Notes Ttspd Typ Max Unit Notes Page [+] Feedback ...
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... Ordering Information Ordering Code CY7C68000A-56LFXC CY7C68000A-56BAXC CY7C68000A-56LTXC CY7C68000A-56LTXCT CY3683 Package Diagrams The MoBL-USB TX2 is available in two packages: 56-pin QFN ■ 56-pin VFBGA ■ Figure 6. 56-Pin Quad Flatpack No Lead Package (Sawn Version) Document #: 38-08052 Rev. *H Package Type 56 QFN 56 VFBGA 56 QFN 56 QFN MoBL-USB TX2 Development Board ...
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... Maintain a solid ground plane under the DPLUS and DMINUS ■ traces. Do not split the plane under these traces Do not place vias on the DPLUS or DMINUS trace routing ■ Isolate the DPLUS and DMINUS traces from all other signal ■ traces by no less than 10 mm CY7C68000A A1 CORNER ...
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... Solder Mask Cu Fill Cu Fill 0.013” dia PCB Material This figure only shows the top three layers of the circuit board: Top Solder, PCB Dielectric, and the Ground Plane Figure 9. Plot of the Solder Mask (White Area) CY7C68000A website, by following this Page link: [+] Feedback ...
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... Document History Page Document Title: CY7C68000A MoBL-USB™ TX2 USB 2.0 UTMI Transceiver Document Number: 38-08052 Orig. of Submission REV. ECN NO. Change ** 285592 KKU See ECN *A 427959 TEH See ECN *B 470121 TEH See ECN *C 476107 TEH See ECN *D 491668 TEH See ECN ...