CYV15G0101DXB-BBC Cypress Semiconductor Corp, CYV15G0101DXB-BBC Datasheet - Page 27
![IC TXRX HOTLINK 100-LBGA](/photos/16/3/160306/bga100_sml.jpg)
CYV15G0101DXB-BBC
Manufacturer Part Number
CYV15G0101DXB-BBC
Description
IC TXRX HOTLINK 100-LBGA
Manufacturer
Cypress Semiconductor Corp
Series
HOTlink II™r
Type
Transceiverr
Datasheet
1.CYP15G0101DXB-BBXC.pdf
(39 pages)
Specifications of CYV15G0101DXB-BBC
Package / Case
100-LBGA
Protocol
Fibre Channel
Voltage - Supply
3.135 V ~ 3.465 V
Mounting Type
Surface Mount
Product
PHY
Supply Voltage (min)
3.135 V
Supply Current
0.5 A
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Number Of Channels
1
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Drivers/receivers
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CYV15G0101DXB-BBC
Manufacturer:
CYPRESS
Quantity:
850
Company:
Part Number:
CYV15G0101DXB-BBC
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Document #: 38-02031 Rev. *J
Switching Waveforms for the HOTLink II Transmitter
Notes:
41. When REFCLK is configured for half-rate operation (TXRATE
42. The TXCLKO output is at twice the rate of REFCLK when TXRATE = HIGH and same rate as REFCLK when TXRATE = LOW. TXCLKO does not follow the
43. The rising edge of TXCLKO output has no direct phase relationship to the REFCLK input.
Transmit Interface
Write Timing
TXCKSEL = LOW
TXRATE = LOW
Transmit Interface
Write Timing
TXCKSEL = LOW
TXRATE = HIGH
Transmit Interface
TXCLKO Timing
TXCKSEL = LOW
TXRATE = HIGH
TXCT[1:0],
TXCT[1:0],
Transmit Interface
Write Timing
TXCKSEL ≠ LOW
TXD[7:0],
TXD[7:0],
is captured using both the rising and falling edges of REFCLK.
duty cycle of REFCLK.
REFCLK
TXCT[1:0],
SCSEL
TXCLK
SCSEL
TXD[7:0],
TXOP,
TXOP,
REFCLK
SCSEL
TXOP,
REFCLK
TXCLKO
Note 43
Note 41
t
t
t
REFH
TXCLKH
TREFDH
t
TXCLKOD+
t
t
REFCLK
TXCLK
t
t
REFH
TXCLKO
=
t
REFH
HIGH) and data is captured using REFCLK instead of TXCLK clock (TXCKSEL
t
TREFDS
t
t
TXCLKL
REFL
t
Note 42
t
TXCLKOD–
TXDS
t
TREFDS
t
REFCLK
Note 41
t
REFCLK
t
t
TREFDH
TXDH
t
TREFDH
t
REFL
t
REFL
CYW15G0101DXB
CYV15G0101DXB
CYP15G0101DXB
t
TREFDS
Page 27 of 39
=
LOW), data
[+] Feedback