ATTINY12-8SU Atmel, ATTINY12-8SU Datasheet
ATTINY12-8SU
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ATTINY12-8SU Summary of contents
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... Nonvolatile Program and Data Memory – 1K Byte of Flash Program Memory In-System Programmable (ATtiny12) Endurance: 1,000 Write/Erase Cycles (ATtiny11/12) – 64 Bytes of In-System Programmable EEPROM Data Memory for ATtiny12 Endurance: 100,000 Write/Erase Cycles – Programming Lock for Flash Program and EEPROM Data Security • ...
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... Flash EEPROM ATtiny11L 1K - ATtiny11 1K - ATtiny12V ATtiny12L ATtiny12 The ATtiny11/12 AVR is supported with a full suite of program and system development tools including: macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits. Register Voltage Range Frequency 32 2.7 - 5.5V 0-2 MHz 32 4.0 - 5.5V 0-6 MHz 32 1 ...
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... The device is manufactured using Atmel’s high-density nonvolatile memory technology. By combining an RISC 8-bit CPU with Flash on a monolithic chip, the Atmel ATtiny11 is a powerful microcontroller that provides a highly-flexible and cost-effective solution to many embedded control applications. ...
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... ATtiny12 Block Diagram ATtiny11/12 4 Figure 2 on page 4. The ATtiny12 provides the following features: 1K bytes of Flash, 64 bytes EEPROM six general-purpose I/O lines, 32 general-purpose working regis- ters, an 8-bit timer/counter, internal and external interrupts, programmable Watchdog Timer with internal oscillator, and two software-selectable power-saving modes. The Idle Mode stops the CPU while allowing the timer/counters and interrupt system to con- tinue functioning ...
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... Ground pin. Port 6-bit I/O port. PB4..0 are I/O pins that can provide internal pull-ups (selected for each bit). On ATtiny11, PB5 is input only. On ATtiny12, PB5 is input or open-drain output. The port pins are tri-stated when a reset condition becomes active, even if the clock is not running. The use of pins PB5..3 as input or I/O pins is limited, depending on reset and clock settings, as shown below ...
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Architectural Overview ATtiny11/12 6 The fast-access register file concept contains 32 x 8-bit general-purpose working regis- ters with a single-clock-cycle access time. This means that during one single clock cycle, one ALU (Arithmetic Logic Unit) operation is executed. Two operands ...
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... A4, followed by four subroutine or interrupt returns, will pop A4, A3, A2, and once more A2 from the hardware stack. ATtiny11/12 Status Control and Test Registers Interrupt Unit General- SPI Unit purpose (ATtiny12 only) Registers 8-bit Timer/Counter Watchdog Timer ALU Analog Comparator I/O Lines EEPROM (ATtiny12 only ...
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General-purpose Register File ATtiny11/12 8 Figure 4 shows the structure of the 32 general-purpose registers in the CPU. Figure 4. AVR CPU General-purpose Working Registers 7 General- purpose Working Registers R30 (Z-register low byte) R31 (Z-register high byte) All the ...
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Status Register Status Register – SREG 1006F–AVR–06/07 The AVR status register (SREG) at I/O space location $3F is defined as: Bit $ Read/Write R/W R/W R/W Initial Value • Bit 7 ...
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... Table 8 on page 23 and Table 10 on page 25. The internal RC oscillator option is an on-chip oscillator running at a fixed frequency of 1 MHz in ATtiny11 and 1.2 MHz in ATtiny12. If selected, the device can operate with no external components. The device is shipped with this option selected. On ATtiny11, the Watchdog Oscillator is used as a clock, while ATtiny12 uses a separate calibrated oscillator ...
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External Clock External RC Oscillator 1006F–AVR–06/07 To drive the device from an external clock source, XTAL1 should be driven as shown in Figure 6. Figure 6. External Clock Drive Configuration EXTERNAL OSCILLATOR SIGNAL For timing insensitive applications, the external RC ...
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Register Description Oscillator Calibration Register – OSCCAL ATtiny11/12 12 Bit $31 CAL7 CAL6 CAL5 Read/Write R/W R/W R/W Initial Value • Bits 7..0 - CAL7..0: Oscillator Calibration Value Writing the calibration byte to this ...
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... ATtiny11/12 $31 OSCCAL ATtiny12 $21 WDTCR ATtiny11/12 $1E EEAR ATtiny12 $1D EEDR ATtiny12 $1C EECR ATtiny12 $18 PORTB ATtiny11/12 $17 DDRB ATtiny11/12 $16 PINB ATtiny11/12 $08 ACSR ATtiny11/12 Note: Reserved and unused locations are not shown in the table. All the different ATtiny11/12 I/O and peripherals are placed in the I/O space. The differ- ent I/O locations are accessed by the IN and OUT instructions transferring data between the 32 general-purpose working registers and the I/O space ...
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Register Direct, Single Register Rd Register Indirect Register Direct, Two Registers Rd and Rr ATtiny11/12 14 Figure 8. Direct Single-register Addressing The operand is contained in register d (Rd). Figure 9. Indirect Register Addressing The register accessed is the one ...
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I/O Direct Relative Program Addressing, RJMP and RCALL Constant Addressing Using the LPM Instruction 1006F–AVR–06/07 Figure 11. I/O Direct Addressing Operand address is contained in 6 bits of the instruction word the destination or source register address. Figure ...
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Memory Access and Instruction Execution Timing ATtiny11/12 16 This section describes the general access timing concepts for instruction execution and internal memory access. The AVR CPU is driven by the System Clock Ø, directly generated from the external clock crystal ...
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... See “Memory Programming” on page 48 for a detailed description on Flash memory programming. The ATtiny12 contains 64 bytes of data EEPROM memory organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endur- ance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described on page 18, specifying the EEPROM Address Register, the EEPROM Data Register, and the EEPROM Control Register ...
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... Bit 7..4 - Res: Reserved Bits These bits are reserved bits in the ATtiny12 and will always read as zero. • Bit 3 - EERIE: EEPROM Ready Interrupt Enable When the I-bit in SREG and EERIE are set (one), the EEPROM Ready interrupt is enabled. When cleared (zero), the interrupt is disabled. The EEPROM Ready interrupt generates a constant interrupt when EEWE is cleared (zero). • ...
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EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 2 and 3 is unessential): 1. Wait until EEWE becomes zero. 2. Write new EEPROM address to EEAR (optional). ...
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... Sleep Modes Sleep Modes for the ATtiny11 Idle Mode Power-down Mode Sleep Modes for the ATtiny12 Idle Mode Power-down Mode ATtiny11/ enter the sleep modes, the SE bit in MCUCR must be set (one) and a SLEEP instruc- tion must be executed. The SM bit in the MCUCR register selects which sleep mode (Idle or Power-down) will be activated by the SLEEP instruction ...
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MCU. Note that if a level triggered or pin change interrupt is used for wake-up from Power- down Mode, the changed level ...
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... The circuit diagram in Figure 15 shows the reset logic for the ATtiny11. Figure 16 shows the reset logic for the ATtiny12. Table 7 defines the electrical parameters of the reset circuitry for ATtiny11. Table 9 shows the parameters of the reset circuitry for ATtiny12 ...
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Power-on Reset for the ATtiny11 1006F–AVR–06/07 A Power-on Reset (POR) circuit ensures that the device is reset from power-on. As shown in Figure 15, an internal timer is clocked from the watchdog timer. This timer pre- vents the MCU from ...
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... ATtiny11/12 24 Figure 16. Reset Logic for the ATtiny12 Power-on Reset Circuit Brown-out BODEN Reset Circuit BODLEVEL On-chip RC Oscillator Table 9. Reset Characteristics for the ATtiny12 Symbol Parameter Power-on Reset Threshold Voltage (rising) (1) V POT Power-on Reset Threshold Voltage (falling) RESET Pin Threshold V RST ...
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... Table 10. ATtiny12 Clock Options and Start-up Times CKSEL3..0 Clock Source 1111 Ext. Crystal/Ceramic Resonator 1110 Ext. Crystal/Ceramic Resonator 1101 Ext. Crystal/Ceramic Resonator 1100 Ext. Crystal/Ceramic Resonator 1011 Ext. Crystal/Ceramic Resonator 1010 Ext. Crystal/Ceramic Resonator 1001 Ext. Low-frequency Crystal 1000 Ext ...
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... Power-on Reset for the ATtiny12 ATtiny11/ Power-on Reset (POR) pulse is generated by an on-chip detection circuit. The detec- tion level is nominally 1.4V. The POR is activated whenever V level. The POR circuit can be used to trigger the start-up reset, as well as detect a fail- ure in supply voltage. ...
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... RST TIME-OUT INTERNAL RESET ATtiny12 has an on-chip brown-out detection (BOD) circuit for monitoring the V during the operation. The BOD circuit can be enabled/disabled by the fuse BODEN. When BODEN is enabled (BODEN programmed), and V level, the brown-out reset is immediately activated. When V ger level, the brown-out reset is deactivated after a delay. The delay is defined by the user in the same way as the delay of POR signal, in Table 14 ...
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Watchdog Reset Register Description MCU Status Register – MCUSR of the ATtiny11 ATtiny11/12 28 When the Watchdog times out, it will generate a short reset pulse cycle dura- tion. On the falling edge of this pulse, the ...
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... Bit 7..4 - Res: Reserved Bits These bits are reserved bits in the ATtiny12 and always read as zero. • Bit 3 - WDRF: Watchdog Reset Flag This bit is set if a watchdog reset occurs. The bit is reset by a power-on reset writ- ing a logic zero to the flag. ...
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... Reset and Interrupt ATtiny11/12 30 The ATtiny11 provides four different interrupt sources and the ATtiny12 provides five. These interrupts and the separate reset vector each have a separate program vector in the program memory space. All the interrupts are assigned individual enable bits which must be set (one) together with the I-bit in the status register in order to enable the interrupt ...
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... If an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed before the interrupt is served. In ATtiny12 interrupt occurs when the MCU is in Sleep mode, the interrupt response time is increased by 4 clock cycles. A return from an interrupt handling routine takes 4 clock cycles. During these 4 clock cycles, the Program Counter (9 bits) is popped back from the Stack, and the I-flag in SREG is set ...
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... Note: The Pull-up Disable (PUD) bit is only available in ATtiny12. • Bit 7 - Res: Reserved Bit This bit is a reserved bit in the ATtiny11/12 and always reads as zero. • Bit 6 - Res: Reserved Bit in ATtiny11 This bit is a reserved bit in the ATtiny11 and always reads as zero. ...
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General Interrupt Mask Register – GIMSK 1006F–AVR–06/07 • Bits ISC01, ISC00: Interrupt Sense Control0 Bit 1 and Bit 0 The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding ...
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General Interrupt Flag Register – GIFR Timer/Counter Interrupt Mask Register – TIMSK ATtiny11/12 34 Bit $3A - INTF0 PCIF Read/Write R R/W R/W Initial Value • Bit 7 - Res: Reserved Bit This bit ...
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Timer/Counter Interrupt Flag Register – TIFR 1006F–AVR–06/07 Bit Read/Write R R Initial Value 0 0 • Bits 7..2 - Res: Reserved Bits These bits are reserved bits in the ATtiny11/12 and always read as zero. ...
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... I/O pins. All I/O pins have individually selectable pull-ups. The Port B output buffers on PB0 to PB4 can sink 20 mA and thus drive LED displays directly. On ATtiny12, PB5 can sink 12 mA. When pins PB0 to PB4 are used as inputs and are externally pulled low, they will source current (I activated ...
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... Pull-up Disable (PUD) bit in the MCUCR register. To switch the pull- up resistor off, the PORTBn can be cleared (zero), the pin can be configured as an out- put pin ATtiny12, the PUD bit can be set. The port pins are tri-stated when a reset condition becomes active, even if the clock is not running. ...
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... RESET - Port B, Bit 5 When the RSTDISBL fuse is unprogrammed, this pin serves as external reset. When the RSTDISBL fuse is programmed, this pin is a general input pin. In ATtiny12 also an open-drain output pin. • XTAL2 - Port B, Bit 4 XTAL2, oscillator output. When this pin is not used for clock purposes general I/O pin. Refer to section “ ...
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Timer/Counter0 Timer/Counter Prescaler 1006F–AVR–06/07 The ATtiny11/12 provides one general-purpose 8-bit Timer/Counter – Timer/Counter0. The Timer/Counter0 has prescaling selection from the 10-bit prescaling timer. The Timer/Counter0 can either be used as a timer with an internal clock timebase ...
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ATtiny11/12 40 Figure 23. Timer/Counter0 Block Diagram T0 1006F–AVR–06/07 ...
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Register Description Timer/Counter0 Control Register – TCCR0 Timer Counter 0 – TCNT0 1006F–AVR–06/07 Bit $ Read/Write Initial Value • Bits 7..3 - Res: Reserved Bits These bits are ...
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Timer/Counter Interrupt Mask Register – TIMSK Timer/Counter Interrupt Flag Register – TIFR ATtiny11/12 42 Bit $ Read/Write Initial Value • Bit 7..2 - Res: Reserved Bits These bits ...
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Watchdog Timer Register Description Watchdog Timer Control Register – WDTCR 1006F–AVR–06/07 The Watchdog Timer is clocked from a separate on-chip oscillator. By controlling the Watchdog Timer prescaler, the Watchdog reset interval can be adjusted as shown in Table 19. See ...
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ATtiny11/ the same operation, write a logical one to WDTOE and WDE. A logical one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four ...
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... Otherwise an interrupt can occur when the bit is changed. • Bit 6 - AINBG: Analog Comparator Bandgap Select in ATtiny12 In ATtiny12, when this bit is set, a fixed bandgap voltage of 1.22 ± 0.05V replaces the normal input to the positive input (AIN0) of the comparator. When this bit is cleared, the normal input pin PB0 is applied to the positive input of the comparator. • ...
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ATtiny11/12 46 • Bit 4 - ACI: Analog Comparator Interrupt Flag This bit is set (one) when a comparator output event triggers the interrupt mode defined by ACI1 and ACI0. The Analog Comparator Interrupt routine is executed if the ACIE ...
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... Voltage Reference Enable Signals and Start-up Time 1006F–AVR–06/07 ATtiny12 features an internal voltage reference with a nominal voltage of 1.22V. This reference is used for Brown-out Detection, and it can be used as an input to the Analog Comparator. The voltage reference has a start-up time that may influence the way it should be used. ...
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... Serial programming modes. Changing the fuses does not have any effect while in pro- gramming mode. • The BODLEVEL Fuse selects the Brown-out Detection level and changes the start- up times. See “Brown-out Detection (ATtiny12)” on page 27. See Table 10, “ATtiny12 Clock Options and Start-up Times,” on page 25. Default value is programmed (“0”). • ...
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... Note the RSTDISBL Fuse is programmed, then the programming hardware should apply +12V to PB5 while the ATtiny12 is in Power-on Reset. If not, the part can fail to enter programming mode caused by drive contention on PB0 and/or PB5. All Atmel microcontrollers have a three-byte signature code which identifies the device. ...
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... High-voltage Serial Programming ATtiny11/12 50 provides a convenient way to download program and data into the ATtiny12 inside the user’s system. The program and data memory arrays in the ATtiny12 are programmed byte-by-byte in either programming mode. For the EEPROM, an auto-erase cycle is provided within the self-timed write instruction in the Low-voltage Serial Programming mode ...
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... The write instruction is self-timed, wait until the PB2 (RDY/BSY) pin goes high. 3. The EEPROM array (ATtiny12 only) is programmed one byte at a time by supply- ing first the address, then the data byte. The write instruction is self-timed, wait until the PB2 (RDY/BSY) pin goes high ...
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... PB1 High byte PB2 x_xxxx_xxxx_xx PB0 0_0001_0001_00 Write EEPROM Low Address PB1 0_0100_1100_00 (ATtiny12) PB2 x_xxxx_xxxx_xx PB0 i_i _00 Write EEPROM PB1 0_0010_1100_00 byte (ATtiny12) PB2 x_xxxx_xxxx_xx PB0 0_0000_0011_00 Read EEPROM Low Address PB1 0_0100_1100_00 (ATtiny12) PB2 x_xxxx_xxxx_xx ATtiny11/12 52 MSB MSB 1 2 ...
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... Table 23. High-voltage Serial Programming Instruction Set for ATtiny11/12 (Continued) Instruction Instr.1 PB0 0_0000_0000_00 Read EEPROM PB1 0_0110_1000_00 byte (ATtiny12) PB2 x_xxxx_xxxx_xx PB0 0_0100_0000_00 Write Fuse bits PB1 0_0100_1100_00 (ATtiny11) PB2 x_xxxx_xxxx_xx PB0 0_0100_0000_00 Write Fuse bits PB1 0_0100_1100_00 (ATtiny12) PB2 x_xxxx_xxxx_xx ...
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... High-voltage Serial Programming Characteristics Low-voltage Serial Downloading (ATtiny12 only) ATtiny11/12 54 Figure 28. High-voltage Serial Programming Timing SDI (PB0), SII (PB1) SCI (PB3) SDO (PB2) Table 24. High-voltage Serial Programming Characteristics T 5.0V ± 10% (Unless otherwise noted) Symbol Parameter t SCI (PB3) Pulse Width High SHSL ...
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... When writing serial data to the ATtiny12, data is clocked on the rising edge of SCK. When reading data from the ATtiny12, data is clocked on the falling edge of SCK. See Figure 30, Figure 31 and Table 26 for timing details. To program and verify the ATtiny12 in the serial programming mode, the following sequence is recommended (See 4 byte instruction formats in Table 25): 1 ...
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Data Polling ATtiny11/12 56 next instruction. See Table 28 on page 58 for t an erased device, no $FFs in the data file(s) needs to be programmed. 6. Any memory location can be verified by using the Read instruction which ...
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Table 25. Low-voltage Serial Programming Instruction Set Instruction Byte 1 1010 1100 Programming Enable 1010 1100 Chip Erase 0010 H000 Read Program Memory 0100 H000 Write Program Memory Read EEPROM 1010 0000 Memory Write EEPROM 1100 0000 Memory 1010 1100 ...
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Low-voltage Serial Programming Characteristics ATtiny11/12 58 Figure 31. Low-voltage Serial Programming Timing MOSI t OVSH SCK MISO Table 26. Low-voltage Serial Programming Characteristics 2.2 - 5.5V (Unless otherwise noted) CC Symbol Parameter 1/t Oscillator Frequency (V CLCL ...
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... Port B Input Leakage Current I IL I/O Pin Input Leakage Current I IH I/O Pin R I/O Pin Pull-Up I/O 1006F–AVR–06/07 *NOTICE: +0. 1.8V to 5.5V for ATtiny12 (Unless otherwise noted) CC Condition Min Except (XTAL) -0.5 XTAL -0.5 Except (XTAL, RESET) 0 XTAL 0 RESET 0.85 V ...
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... The sum of all I , for all ports, should not exceed 100 mA exceeds the test condition greater than the listed test condition. 5. Minimum V for Power-down is 1.5V. (On ATtiny12: only with BOD disabled) CC ATtiny11/ 1.8V to 5.5V for ATtiny12 (Unless otherwise noted) CC Condition Min Active 1 MHz, V ...
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... Symbol Parameter 1/t Oscillator Frequency CLCL t Clock Period CLCL t High Time CHCX t Low Time CLCX t Rise Time CLCH t Fall Time CHCL External Clock Drive ATtiny12 V CC Symbol Parameter Min Oscillator 1/t Frequency 0 CLCL t Clock Period 833 CLCL t High Time 333 CHCX t ...
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ATtiny11 Typical Characteristics ATtiny11/12 62 The following charts show typical behavior. These figures are not tested during manu- facturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave ...
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Figure 34. Active Supply Current vs. V ACTIVE SUPPLY CURRENT vs 2.5 3 Figure 35. Active Supply Current vs. V ACTIVE SUPPLY CURRENT vs. V DEVICE ...
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ATtiny11/12 64 Figure 36. Active Supply Current vs. V ACTIVE SUPPLY CURRENT vs. V DEVICE CLOCKED BY 32KHz CRYSTAL 5 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 2.5 3 3.5 Figure 37. Idle Supply Current vs. Frequency ...
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Figure 38. Idle Supply Current vs. V IDLE SUPPLY CURRENT vs 2.5 3 Figure 39. Idle Supply Current vs. V IDLE SUPPLY CURRENT vs. V DEVICE CLOCKED BY 1.0MHz INTERNAL RC ...
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ATtiny11/12 66 Figure 40. Idle Supply Current vs. V IDLE SUPPLY CURRENT vs. V DEVICE CLOCKED BY 32KHz CRYSTAL 2.5 3 3.5 Figure 41. Power-down Supply Current vs. V POWER-DOWN SUPPLY CURRENT vs. V ...
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Figure 42. Power-down Supply Current vs. V POWER-DOWN SUPPLY CURRENT vs. V WATCHDOG TIMER ENABLED 1.5 2 2.5 3 Figure 43. Analog Comparator Current vs. V ANALOG COMPARATOR CURRENT ...
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ATtiny11/12 68 Analog comparator offset voltage is measured as absolute offset. Figure 44. Analog Comparator Offset Voltage vs. Common Mode Voltage ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE ...
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Figure 46. Analog Comparator Input Leakage Current ANALOG COMPARATOR INPUT LEAKAGE CURRENT -10 0 0.5 1 1.5 2 2.5 Figure 47. Watchdog Oscillator Frequency vs. V WATCHDOG OSCILLATOR FREQUENCY vs. V 1600 ...
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ATtiny11/12 70 Sink and source capabilities of I/O ports are measured on one pin at a time. Figure 48. Pull-up Resistor Current vs. Input Voltage PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE 120 ˚ A 100 T ...
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Figure 50. I/O Pin Sink Current vs. Output Voltage I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE ˚ ˚ 0.5 ...
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ATtiny11/12 72 Figure 52. I/O Pin Sink Current vs. Output Voltage I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE 0.5 Figure 53. I/O Pin Source ...
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Figure 54. I/O Pin Input Threshold Voltage vs. V I/O PIN INPUT THRESHOLD VOLTAGE vs. V 2.5 2 1.5 1 0.5 0 2.7 Figure 55. I/O Pin Input Hysteresis vs. V I/O PIN INPUT HYSTERESIS vs. V 0.18 0.16 ...
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... ATtiny12 Typical Characteristics ATtiny11/12 74 The following charts show typical behavior. These data are characterized, but not tested. All current consumption measurements are performed with all I/O pins config- ured as inputs and with internal pull-ups enabled. A sine wave generator with rail-to-rail output is used as clock source. ...
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Figure 57. Active Supply Current vs. V ACTIVE SUPPLY CURRENT vs. V DEVICE CLOCKED BY 32KHz CRYSTAL 140 120 100 1.5 2 2.5 3 Figure 58. Idle Supply Current vs. V IDLE SUPPLY CURRENT ...
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ATtiny11/12 76 Figure 59. Idle Supply Current vs. V IDLE SUPPLY CURRENT vs. V DEVICE CLOCKED BY 32KHz CRYSTAL ˚ 1.5 2 2.5 3 ...
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Figure 61. Analog Comparator Offset Voltage vs. Common Mode Voltage ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE 0.5 1 Common Mode Voltage (V) Figure 62. Analog Comparator Input Leakage Current ANALOG ...
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ATtiny11/12 78 Figure 63. Calibrated RC Oscillator Frequency vs. V CALIBRATED RC OSCILLATOR FREQUENCY vs. OPERATING VOLTAGE 1.22 1.2 1.18 1.16 1.14 1.12 1.1 1.08 1.06 2 2.5 3 3.5 Figure 64. Watchdog Oscillator Frequency vs. V WATCHDOG OSCILLATOR FREQUENCY ...
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Sink and source capabilities of I/O ports are measured on one pin at a time. Figure 65. Pull-up Resistor Current vs. Input Voltage (V 120 ˚ A 100 ˚ ...
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ATtiny11/12 80 Figure 67. I/O Pin Sink Current vs. Output Voltage ( 0.5 1 Figure 68. I/O Pin Source Current vs. Output Voltage ( ˚ A ...
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Figure 69. I/O Pin Sink Current vs. Output Voltage ( 0.5 Figure 70. I/O Pin Source Current vs. Output Voltage ( ˚ ...
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ATtiny11/12 82 Figure 71. I/O Pin Input Threshold Voltage vs. V 2.5 2 1.5 1 0.5 0 2.7 Figure 72. I/O Pin Input Hysteresis vs. V 0.18 0.16 0.14 0.12 0.1 0.08 0.06 0.04 0. 25°C) ...
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Register Summary ATtiny11 Address Name Bit 7 $3F SREG I $3E Reserved $3D Reserved $3C Reserved $3B GIMSK - $3A GIFR - $39 TIMSK - $38 TIFR - $37 Reserved $36 Reserved $35 MCUCR - $34 MCUSR - $33 TCCR0 ...
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... Register Summary ATtiny12 Address Name Bit 7 $3F SREG I $3E Reserved $3D Reserved $3C Reserved $3B GIMSK - $3A GIFR - $39 TIMSK - $38 TIFR - $37 Reserved $36 Reserved $35 MCUCR - $34 MCUSR - $33 TCCR0 - $32 TCNT0 Timer/Counter0 (8 Bit) $31 OSCCAL Oscillator Calibration Register $30 Reserved ... Reserved $22 Reserved $21 WDTCR - $20 Reserved $1F Reserved $1E EEAR - $1D EEDR EEPROM Data Register $1C EECR - $1B Reserved ...
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Instruction Set Summary Mnemonics Operands Description ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers ADC Rd, Rr Add with Carry two Registers SUB Rd, Rr Subtract two Registers SUBI Rd, K Subtract Constant from Register SBC Rd, Rr ...
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Instruction Set Summary (Continued) Mnemonics Operands Description DATA TRANSFER INSTRUCTIONS LD Rd,Z Load Register Indirect ST Z,Rr Store Register Indirect MOV Rd, Rr Move Between Registers LDI Rd, K Load Immediate IN Rd Port OUT P, Rr Out ...
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Ordering Information ATtiny11 Power Supply Speed (MHz) 2.7 - 5.5V 4.0 - 5.5V Notes: 1. The speed grade refers to maximum clock rate when using an external crystal or external clock drive. The internal RC oscil- lator has the same ...
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... ATtiny12L-4SU 8S2 ATtiny12-8PC 8P3 ATtiny12-8SC 8S2 ATtiny12-8PI 8P3 (2) ATtiny12-8PU 8P3 ATtiny12-8SI 8S2 (2) ATtiny12-8SU 8S2 Package Type Operation Range Commercial (0°C to 70°C) Industrial (-40°C to 85°C) Commercial (0°C to 70°C) Industrial (-40°C to 85°C) Commercial (0°C to 70°C) Industrial (-40°C to 85°C) ...
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Packaging Information 8P3 Top View PLCS Side View Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information. 2. Dimensions A and L are measured with the ...
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Notes: 1. This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information. 2. Mismatch of the upper and lower dies and resin burrs are not included recommended that upper ...
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... Updated chapter layout. 2. Updated Power-down in “Sleep Modes for the ATtiny11” on page 20. 3. Updated Power-down in “Sleep Modes for the ATtiny12” on page 20. 4. Updated Table 16 on page 36. 5. Updated “Calibration Byte in ATtiny12” on page 49. ...
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... Memory Access and Instruction Execution Timing ............................................. 13 I/O Memory ......................................................................................................... 14 Reset and Interrupt Handling.............................................................................. 15 ATtiny12 Internal Voltage Reference.................................................................. 24 Interrupt Handling ............................................................................................... 25 Sleep Modes for the ATtiny11 ............................................................................ 31 Sleep Modes for the ATtiny12 ............................................................................ 31 ATtiny12 Calibrated Internal RC Oscillator ......................................................... 32 Timer/Counter0 ................................................................................... 33 Timer/Counter Prescaler..................................................................................... 33 Watchdog Timer.................................................................................. 36 ATtiny12 EEPROM Read/Write Access............................................. 38 Prevent EEPROM Corruption ...
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... ATtiny11/12 ii High-voltage Serial Programming Algorithm....................................................... 49 High-voltage Serial Programming Characteristics .............................................. 52 Low-voltage Serial Downloading (ATtiny12 only) ............................................... 52 Low-voltage Serial Programming Characteristics............................................... 56 Electrical Characteristics................................................................... 57 Absolute Maximum Ratings ................................................................................ 57 DC Characteristics – Preliminary Data ............................................................... 57 External Clock Drive Waveforms ........................................................................ 59 External Clock Drive ATtiny11 ............................................................................ 59 External Clock Drive ATtiny12 ............................................................................ 59 ATtiny11 Typical Characteristics ........................................................................ 60 ATtiny12 Typical Characteristics ...
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