ATTINY12-8SU Atmel, ATTINY12-8SU Datasheet - Page 46

• Manufacturer Part Number: ATTINY12-8SU
• Description: Microcontrollers (MCU) AVR 1K FLASH 64B EE 5V 8MHZ
• Manufacturer: Atmel

Specifications of ATTINY12-8SU

• Processor Series: ATTINY1x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 1 KB
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 6
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500
• Minimum Operating Temperature: - 40 C
• Cpu Family: ATtiny
• Device Core: AVR
• Device Core Size: 8b
• Frequency (max): 8MHz
• Interface Type: SPI
• # I/os (max): 6
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 8
• Package Type: SOIC EIAJ
• Lead Free Status / Rohs Status: Details

46
ATtiny11/12
• Bit 4 - ACI: Analog Comparator Interrupt Flag
This bit is set (one) when a comparator output event triggers the interrupt mode defined
by ACI1 and ACI0. The Analog Comparator Interrupt routine is executed if the ACIE bit
is set (one) and the I-bit in SREG is set (one). ACI is cleared by hardware when execut-
ing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a
logic one to the flag.
• Bit 3 - ACIE: Analog Comparator Interrupt Enable
When the ACIE bit is set (one) and the I-bit in the Status Register is set (one), the Ana-
log Comparator Interrupt is activated. When cleared (zero), the interrupt is disabled.
• Bit 2 - Res: Reserved Bit
This bit is a reserved bit in the ATtiny11/12 and will always read as zero.
• Bits 1,0 - ACIS1, ACIS0: Analog Comparator Interrupt Mode Select
These bits determine which comparator events that trigger the Analog Comparator Inter-
rupt. The different settings are shown in Table 20.
Table 20. ACIS1/ACIS0 Settings
Note:
Caution: Using the SBI or CBI instruction on bits other than ACI in this register will write
a one back into ACI if it is read as set, thus clearing the flag.
ACIS1
0
0
1
1
When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be dis-
abled by clearing its interrupt enable bit in the ACSR register. Otherwise, an interrupt can
occur when the bits are changed.
ACIS0
0
1
0
1
Comparator Interrupt on Output Toggle
Reserved
Comparator Interrupt on Falling Output Edge
Comparator Interrupt on Rising Output Edge
Interrupt Mode
1006F–AVR–06/07