ATTINY12L-4SU Atmel, ATTINY12L-4SU Datasheet - Page 19

• Manufacturer Part Number: ATTINY12L-4SU
• Description: Microcontrollers (MCU) AVR 1K FLASH 64B EE 3V 4MHZ
• Manufacturer: Atmel

Specifications of ATTINY12L-4SU

• Processor Series: ATTINY1x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 1 KB
• Maximum Clock Frequency: 4 MHz
• Number Of Programmable I/os: 6
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500
• Minimum Operating Temperature: - 40 C
• Package: 8SOIC EIAJ
• Device Core: AVR
• Family Name: ATtiny
• Maximum Speed: 4 MHz
• Operating Supply Voltage: 3.3|5 V
• Interface Type: SPI
• Operating Temperature: -40 to 85 °C
• Lead Free Status / Rohs Status: Details

1006F–AVR–06/07
otherwise no EEPROM write takes place. The following procedure should be followed
when writing the EEPROM (the order of steps 2 and 3 is unessential):
1. Wait until EEWE becomes zero.
2. Write new EEPROM address to EEAR (optional).
3. Write new EEPROM data to EEDR (optional).
4. Write a logical one to the EEMWE bit in EECR (to be able to write a logical one
5. Within four clock cycles after setting EEMWE, write a logical one to EEWE.
Caution: An interrupt between step 4 and step 5 will make the write cycle fail, since the
EEPROM Master Write Enable will time-out. If an interrupt routine accessing the
EEPROM is interrupting another EEPROM access, the EEAR or EEDR register will be
modified, causing the interrupted EEPROM access to fail. It is recommended to have
the global interrupt flag cleared during the four last steps to avoid these problems.
When the write access time has elapsed, the EEWE bit is cleared (zero) by hardware.
The user software can poll this bit and wait for a zero before writing the next byte. When
EEWE has been set, the CPU is halted for two cycles before the next instruction is
executed.
• Bit 0 - EERE: EEPROM Read Enable
The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the
correct address is set up in the EEAR register, the EERE bit must be set. When the
EERE bit is cleared (zero) by hardware, requested data is found in the EEDR register.
The EEPROM read access takes one instruction and there is no need to poll the EERE
bit. When EERE has been set, the CPU is halted for four cycles before the next instruc-
tion is executed.
The user should poll the EEWE bit before starting the read operation. If a write operation
is in progress when new data or address is written to the EEPROM I/O registers, the
write operation will be interrupted, and the result is undefined.
The calibrated oscillator is used to time EEPROM. In Table 6 the typical programming
time is listed for EEPROM access from the CPU.
Table 6. Typical EEPROM Programming Times
Parameter
EEPROM write
to the EEMWE bit, the EEWE bit must be written to zero in the same cycle).
(from CPU)
Number of Calibrated
RC Oscillator Cycles
4096
Min Programming
Time
3.1 ms
ATtiny11/12
Max Programming
Time
6.8 ms
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