MC9S12E128CPV Freescale Semiconductor, MC9S12E128CPV Datasheet - Page 192
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MC9S12E128CPV
Manufacturer Part Number
MC9S12E128CPV
Description
Microcontrollers (MCU) 16 Bit 16MHz
Manufacturer
Freescale Semiconductor
Datasheet
1.MC9S12E128CPV.pdf
(606 pages)
Specifications of MC9S12E128CPV
Data Bus Width
16 bit
Program Memory Type
Flash
Program Memory Size
128 KB
Data Ram Size
8 KB
Interface Type
SCI, SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
92
Number Of Timers
16 bit
Operating Supply Voltage
3.135 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
LQFP-112
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
On-chip Dac
8 bit, 2 Channel
Lead Free Status / Rohs Status
No RoHS Version Available
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S12E128CPVE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Chapter 4 Clocks and Reset Generator (CRGV4)
4.4.10
All clocks are stopped in STOP mode, dependent of the setting of the PCE, PRE and PSTP bit. The
oscillator is disabled in STOP mode unless the PSTP bit is set. All counters and dividers remain frozen but
do not initialize. If the PRE or PCE bits are set, the RTI or COP continues to run in pseudo-stop mode. In
addition to disabling system and core clocks the CRG requests other functional units of the MCU (e.g.
voltage-regulator) to enter their individual power-saving modes (if available). This is the main difference
between pseudo-stop mode and wait mode.
After executing the STOP instruction the core requests the CRG to switch the MCU into stop mode. If the
PLLSEL bit remains set when entering stop mode, the CRG will switch the system and core clocks to
OSCCLK by clearing the PLLSEL bit. Then the CRG disables the PLL, disables the core clock and finally
disables the remaining system clocks. As soon as all clocks are switched off, stop mode is active.
If pseudo-stop mode (PSTP = 1) is entered from self-clock mode the CRG will continue to check the clock
quality until clock check is successful. The PLL and the voltage regulator (VREG) will remain enabled. If
full stop mode (PSTP = 0) is entered from self-clock mode an ongoing clock quality check will be stopped.
A complete timeout window check will be started when stop mode is exited again.
Wake-up from stop mode also depends on the setting of the PSTP bit.
192
CME
1
SCME
1
Low-Power Operation in Stop Mode
SCMIE
1
Table 4-11. Outcome of Clock Loss in Wait Mode (continued)
Clock failure -->
– VREG enabled,
– PLL enabled,
– SCM activated,
– Start Clock Quality Check,
– SCMIF set.
SCMIF generates Self-Clock Mode wakeup interrupt.
– Exit Wait Mode in SCM using PLL clock (f
– Continue to perform a additional Clock Quality Checks until OSCCLK
is o.k. again.
MC9S12E128 Data Sheet, Rev. 1.07
CRG Actions
SCM
) as system clock,
Freescale Semiconductor
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