ZLF645S0P2064G Zilog, ZLF645S0P2064G Datasheet - Page 61

• Manufacturer Part Number: ZLF645S0P2064G
• Description: Microcontrollers (MCU) 64K Flash 512B RAM 20 pin
• Manufacturer: Zilog

Specifications of ZLF645S0P2064G

• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Data Ram Size: 512 KB
• Interface Type: ICP, UART
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 3
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Package / Case: PDIP-20
• Minimum Operating Temperature: 0 C
• Lead Free Status / Rohs Status: Details

ICP Interface
Enabling ICP Mode
PS026407-0408
State of ZLF645 in ICP Mode
The ICP interface of the ZLF645 is a single pin RS-232 like interface for performing
programming, reads, and memory erasures to the ZLF645’s Flash memory. For enabling
the ZLF645 into ICP mode and for performing ICP operations, the ZLF645’s P34 pin
which normally functions as an output only is used.
As mentioned previously, the ZLF645’s GPIO pin P34 is multi-functioned to be used for
putting the ZLF645 into ICP mode and for ICP communications once it is in that mode.
Entry into ICP mode takes place during the ZLF645’s power on reset period. During the
ZLF645’s power on reset period, the P34 pin which normally is an output only pin is
configured by the ZLF645 as an input with pull-up enabled. If during this time this pin is
driven LOW and held LOW until the end of the power on reset period, the ZLF645 will be
put into ICP mode. Once in ICP mode, the P34 pin operates as an open-drain output
bidirectional pin with pull-up enabled. The power on reset period as can be seen from the
electrical specs section of this document can have a duration range of between 2.5 ms and
10 ms. To ensure proper entry into ICP mode, the P34 pin should be driven LOW and held
low a minimum of 10 ms after power up.
If during the ZLF645’s power on reset period, the P34 pin is never driven LOW, pin p34
will be pulled HIGH through its pull-up device. In this case, if P34 remains HIGH until the
end of the power on reset period, the ZLF645 will go into normal user mode and P34 will
revert back to being an output pin only. To ensure proper entry into user mode when it is
not intended to put the ZLF645 into ICP mode, it is important that in the customer
application P34 only be connected to capacitive loads. This is due to the weak nature of its
pull-up device, which can have a resistance ranging between 100 kΩ up to 600 kΩ
depending on voltage, temperature, and process.
The operating characteristics of the device in ICP mode are:
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The CPU stops executing instructions.
All on-chip peripherals are disabled.
The ZLF645 constantly refreshes the Watchdog Timer, if enabled.
The P34 pin is configured as a bidirectional pin with pull-up enabled and with the
output stage configured as open-drain. The bidirectional control of the pins comes from
the ICP Tx/Rx logic.
ZLF645 Series Flash MCUs
Product Specification
ICP Interface
53