ZLF645S0P2064G Zilog, ZLF645S0P2064G Datasheet - Page 93

• Manufacturer Part Number: ZLF645S0P2064G
• Description: Microcontrollers (MCU) 64K Flash 512B RAM 20 pin
• Manufacturer: Zilog

Specifications of ZLF645S0P2064G

• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Data Ram Size: 512 KB
• Interface Type: ICP, UART
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 3
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Package / Case: PDIP-20
• Minimum Operating Temperature: 0 C
• Lead Free Status / Rohs Status: Details

PS026407-0408
Note:
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Ensure that the transmitter uses the same stop bit configuration as the receiver.
UART Overrun Errors
When an overrun error condition occurs the UART prevents overwriting of the valid data
currently in the Receive Data register. The Break Detect and Overrun status bits are not
displayed until after the valid data has been read.
After the valid data has been read, the UART Status (UST) register is updated to indicate
the overrun condition (and Break Detect, if applicable). The UST[7] bit is set to 1 to
indicate that the Receive Data register contains a data byte. However, because the overrun
error occurred, this byte may not contain valid data and must be ignored. The Break Detect
bit, UST[3], indicates if the overrun was caused by a break condition on the line. After
reading the status byte indicating an overrun error, the Receive Data register must be read
again to clear the error bits is the UART Status 0 register. Updates to the Receive Data reg-
ister occur only when the next data word is received.
UART Data and Error Handling Procedure
Figure 25
interrupt service routine.
immediately if there is no valid data in the Receive Data register. If data is present in
the Receive Data register, an interrupt will occur after the UART Receive Data
register is read.
An overrun is detected—An overrun occurs when a byte of data is received while
there is valid data in the UART Receive Data register that has not been read by the
user. The interrupt will be generated when the user reads the UART Receive Data
register. The interrupt is cleared by reading the UART Receive Data register. When an
overrun error occurs, the additional data byte will not overwrite the data currently
stored in the UART Receive Data register.
A data framing error is detected—A data framing error is detected when the first
stop bit is 0 instead of 1. When configured for 2 stop bits, a data framing error is only
detected when the first stop bit is 0. A framing error interrupt is generated when the
framing error is detected. Reading the UART Receive Data register clears the
interrupt.
on page 86 displays the recommended procedure for use in UART receiver
ZLF645 Series Flash MCUs
Product Specification
Operation
85