MCIMX536AVV8C Freescale Semiconductor, MCIMX536AVV8C Datasheet
MCIMX536AVV8C
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... As the heart of the application chipset, the i.MX53xA processor This document contains information on a new product. Specifications and information herein are subject to change without notice. © 2011 Freescale Semiconductor, Inc. All rights reserved. Document Number: IMX53AEC Rev. 1, 3/2011 MCIMX53xA ...
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... For detailed information about the i.MX53xA security features contact a Freescale representative. The i.MX53xA application processor is a follow-on to the i.MX51xA, with improved performance, power efficiency, and multimedia capabilities. i.MX53xA Automotive and Infotainment Applications Processors, Rev ® ES 2.0 3D graphics accelerator (33 Mtri/s, 200 Mpix/ serial audio, among others). Freescale Semiconductor ...
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... NAND SLC/MLC Flash MHz, 4/8/14/16-bit ECC — 8,16-bit NOR Flash, PSRAM & cellular RAM. — 32-bit multiplexed mode NOR Flash, PSRAM & cellular RAM. — 8-bit Asynchronous (DTACK mode) EIM interface. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Table 1. Ordering Information Features — Introduction ...
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... MP/s (for example, WXGA @ 60 Hz) each. — TV-out/VGA port up to 150 Mpix/s (for example, 1080p60). • Camera sensors: — Two parallel 20-bit camera ports. Primary up to 180-MHz peak clock frequency, secondary up to 120-MHz peak clock frequency. i.MX53xA Automotive and Infotainment Applications Processors, Rev NOTE Freescale Semiconductor ...
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... On-chip oscillator amplifier supporting 32.768 kHz external crystal • On-chip LDO voltage regulators for PLLs Security functions are enabled and accelerated by the following hardware: • ARM TrustZone including the TZ architecture (separation of interrupts, memory mapping, and so on) i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Introduction 5 ...
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... Functions such as video hardware acceleration, 2D and 3D hardware graphics acceleration, and Macrovision enabled for specific part numbers. 2 Architectural Overview The following subsections provide an architectural overview of the i.MX53xA processor system. i.MX53xA Automotive and Infotainment Applications Processors, Rev NOTE TM video copy protection may not be Table 1. Freescale Semiconductor ...
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... Audio, Power Mngmnt. Ethernet 10/100 Mbps IrDA XVR The numbers in brackets indicate number of module instances. For example, PWM (2) indicates two separate PWM peripherals. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor NOR/NAND Battery Ctrl Camera LVDS Camera Flash Device (2) (WSXGA+) (2) ...
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... The security control registers (SCR) of the CSU are set during boot time by the high assurance boot (HAB) code and are locked to prevent further writing. Table 2 describes these Freescale Semiconductor ...
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... Connectivity Audio Interface Peripherals i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Brief Description The debug system provides real-time trace debug capability of both instructions and data. It supports a trace protocol that is an integral part of the ARM Real Time Debug solution (RealView). ...
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... EXTMC environment of a vehicle, cost-effectiveness and required bandwidth. The FLEXCAN is a full implementation of the CAN protocol specification, Version 2.0 B (ISO 11898), which supports both standard and extended message frames at 1 Mbps. Freescale Semiconductor ...
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... IC Identification Security Module i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Brief Description These modules are used for general purpose input/output to external ICs. Each GPIO module supports bits of I/O. Each GPT is a 32-bit “free-running” or “set and forget” mode timer with a programmable prescaler and compare and capture register ...
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... The pulse-width modulator (PWM) has a 16-bit counter and is optimized to generate sound from stored sample audio images. It can also generate tones. The PWM uses 16-bit resolution and data FIFO to generate sound. Brief Description ® data network, using Freescale Semiconductor ...
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... SCCv2 Security Security Controller, ver. 2 i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Brief Description Internal RAM, shared with VPU. The on-chip memory controller (OCRAM) module interface between the system’s AXI bus, to the internal (on-chip) SRAM memory module used for controlling the 128 KB multimedia RAM, through a 64-bit AXI bus. ...
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... JTAG security modes that can be selected through an e-fuse configuration. SPBA (shared peripheral bus arbiter two-to-one IP bus interface (IP bus) arbiter. A standard digital audio transmission protocol developed jointly by the Sony and Philips corporations. Both transmitter and receiver functionalists are supported. Freescale Semiconductor ...
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... ARM/Control Interrupt Controller i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Brief Description The SRTC incorporates a special system state retention register (SSRR) that stores system parameters during system shutdown modes. This register and all SRTC counters are powered by dedicated supply rail NVCC_SRTC_POW ...
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... MJPEG encode, Baseline profile 8192 x 8192 resolution, 80 Mpixel/s bit rate for 4:2:2 format The watch dog timer supports two comparison points during each counting period. Each of the comparison points is configurable to evoke an interrupt to the ARM core, and a second point evokes an external event on the WDOG line Freescale Semiconductor ...
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... This section provides the device-level electrical characteristics for the IC. See to the individual tables and sections. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Brief Description The TrustZone watchdog (TZ WDOG) timer module protects against TrustZone starvation by providing a method of escaping normal mode and forcing a switch to the TZ mode ...
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... Table 5 on page 19 Table 6 on page 19 Table 7 on page 22 Table 8 on page 22 Table 9 on page 24 Table 6 is not Min Max Unit –0.3 1.35 V –0.3 1.35 V –0.5 3.6 V –0.5 3.3 V — 5. –0.3 3. –0.5 OVDD +0 — 2000 — 500 o –40 150 C Freescale Semiconductor ...
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... Peripheral supply voltage VCC Peripheral supply voltage—Stop mode Memory arrays voltage 3 VDDA Memory arrays voltage—Stop mode i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Table 5. Package Thermal Resistance Data Board 1, 2 Single layer board (1s Four layer board (2s2p) ...
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... V 2.775 2.5 2.75 V 2.5 2.75 V 1.8 1.9 1.2 1.3 1.55 1.63 V 1.5 1.58 1.5 1.58 — 3.3 V 1.8 1.95 2.775 3.1 V 3.3 3.6 2.75 2.91 V 1.8 or 3.1 V 2.775 1.3 1.35 V 1.8 or 3.1 V 2.775 2.5 2.75 V 3.3 3.6 V Freescale Semiconductor ...
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... The CKIL is used for low-frequency functions. It supplies the clock for wake-up circuit, power-down real time clock operation, and slow system and watch-dog counters. The clock input can be connected to either external oscillator or a crystal using internal oscillator amplifier. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Parameter Minimum and Table 104 on page 151 2 ...
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... Table 8. Maximal Supply Currents Conditions 800MHz ARM clock. Fuse Write Mode operation 1.8v (DDR2) 1.5v (DDR3) 1.2v (LPDDR2) Typ Max Unit 2 /32.0 — kHz MHz 24 27 MHz Max Current Unit 1450 mA 800 mA 100 325 800 mA 650 mA 250 mA 200 mA Freescale Semiconductor ...
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... General Equation for estimated, maximal power consumption power supply: Imax = (0 Where Number of IO pins supplies by the power line C - Equivalent external capacitive load voltage (0 Data change rate 0.5 of the clock rate (F). i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Conditions Max Current < Use maximal IO Eq ...
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... Automotive and Infotainment Applications Processors, Rev Conditions Typical @ 25 °C RX 5.5 Full Speed High Speed 6.5 Full Speed TX 6 High Speed Full Speed High Speed TX 8 — Suspend Max Unit — — mA — — — μA Freescale Semiconductor ...
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... This is due to ESD diode protection circuit, that may cause current leakage if one of the supplies is powered ON before the other. The POR_B input must be immediately asserted at power-up and remain asserted until after the last power rail reaches its working voltage. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor NOTE Electrical Characteristics 25 ...
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... If fuse writing is required, VDD_FUSE should be powered ON after NVCC_CKIH is stable. i.MX53xA Automotive and Infotainment Applications Processors, Rev 90% 90% Δt > 0 90% Δt > 0 Δt > 0 Δt > 0 90% Δt > 0 90% Figure 2. Power Up Detailed Sequence NOTE 90% 90% Δt > 0 Δt > 0 90% Δt > 0 90% Δt > Freescale Semiconductor ...
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... Double Data Rate 3 I/O (DDR3) for DDR2/LVDDR2, LPDDR2 and DDR3 modes • Low Voltage I/O (LVIO) • Ultra High Voltage I/O (UHVIO) • LVDS I/O i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Assignments.” Electrical Characteristics Section 6, 27 ...
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... Table 6, unless otherwise noted. Min Typ Max OVDD – 0.15 — — 0.8*OVDD — — 0.15 × 0.2 OVDD –0.85 –1.7 — — –2.5 –3.4 0.9 1.9 — — 2.9 3.8 –2.1 –4.2 — — –6.3 –8.4 Freescale Semiconductor Unit ...
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... DDR2 Mode I/O DC Parameters The DDR2 interface fully complies with JESD79-2E DDR2 JEDEC standard release April, 2008. The parameters in Table 11 are guaranteed per the operating ranges in i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Symbol Test Conditions × Iol Vout = 0.2 ...
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... OVDD+0.3 –0.3 — Vref-0.125V –0.3 — OVDD+0.3 0.25 — OVDD+0.6 Vref Vref + 0.04 — 0.07 5 — 2 360 8 — 125 — 1 Min Typ Max — — — — 0.1*OVDD 0.5*OVDD 0.51*OVDD — OVDD Freescale Semiconductor Unit kΩ Unit ...
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... Pull-up/Pull-down impedance mismatch 240 Ω unit calibration resolution Keeper Circuit Resistance 1 OVDD – I/O power supply (1.425 V–1.575 V for DDR3) 2 external reference voltage Vref – DDR3 i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Vil(dc) — Vih(diff) Vil(diff) Iin VI=OVDD — ...
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... OVDD — — 0.5 × OVDD — — — 1.7 250 120 — — 161 0.12 — — 76 0.12 — — 36 0.12 — — 0. — 125 — — 125 — Freescale Semiconductor Unit μA μA μA μA kΩ ...
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... Input current (22 kΩ Pull-up) Input current (75 kΩ Pull-up) Input current (100 kΩ Pull-up) Input current (360 kΩ Pull-down) Keeper Circuit Resistance i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Table Symbol Test Conditions Voh Iout = –1mA OVDD–0.15 Iout= specified Ioh 0 ...
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... Automotive and Infotainment Applications Processors, Rev Symbol Test Conditions V Rload=100Ω OD padP, –padN 1.125 OS NOTE Min Typ Max 250 350 450 1.25 1.375 1.6 0.9 1.025 1.25 1.2 1.375 Figure 4). Freescale Semiconductor Unit mV V ...
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... OVDD Vref1 Vref 0 Vovdd – Vref1 Rpu = Rpd = Vovdd – Vref2 Figure 4. Impedance Matching Load for Measurement i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor OVDD PMOS (Rpu) Ztl Ω inches pad NMOS (Rpd) OVSS Vref2 × Ztl Vref1 Vref2 × ...
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... OVDD 2.775 V OVDD 1.875 V 104 150 134 Typ Max OVDD OVDD OVDD OVDD 1.875 V 3.3 V 1.65 V 3.6 V 114 124 135 198 118 126 154 179 Freescale Semiconductor Unit 250 125 Ω 243 122 Ω Unit 206 Ω 103 69 217 Ω 109 72 ...
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... Output Pad Slew Rate (High Drive) Output Pad Slew Rate (Medium Drive) 1 Output Pad Slew Rate (Low Drive) i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor From Output Test Point Under Test CL CL includes package, probe and fixture capacitance Figure 5. Load Circuit for Output ...
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... Freescale Semiconductor Unit mA/ns ns Unit V/ns V/ns V/ns V/ns mA/ns mA/ns mA/ns mA/ns ns ...
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... AC input logic low 2 AC differential input high voltage AC differential input low voltage Input AC differential cross point voltage Over/undershoot peak Over/undershoot area (above OVDD or below OVSS) i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Symbol Test Condition Vih(ac) — Vil(ac) — Vid(ac) — 3 ...
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... Min Typ Max — OVDD Vref 0.175 0 — – 0.35 — — 0.15 – — Vref + 0.15 0.15 – — Vref + 0.15 2.5 — 5 — — 0.2 0.1 Table 24 and Freescale Semiconductor Unit V/ns ns Unit V/ns ns ...
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... VIL to VIH for rising edge and between VIH to VIL for falling edge. 2 Hysteresis mode is recommended for inputs with transition times greater than 25 ns. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Symbol Test Condition trm — Test ...
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... Max — — 1.72/1.92 3.46/3.70 — — 2.38/2.56 5.07/5.25 — — 4.55/4.58 10.04/9.94 1.05/0.94 — — 0.52/0.49 0.76/0.71 — — 0.36/0.34 0.40/0.93 — — 0.18/0.18 — — 82.8 — — 65.6 — — 43.1 — — Freescale Semiconductor Unit ns V/ns mA/ns ns ...
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... Duration of RESET_IN to be qualified as valid (input slope = 5 ns) 4.6.2 WDOG Reset Timing Parameters Figure 9 shows the WDOG reset timing and WATCHDOG_RST (Input) i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Symbol Test Condition t SKD Rload = 100 Ω, t TLH Cload = 2 pF ...
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... Unit — 40.0 MHz — 0.3 — NVCC_CKIH — VDD Vp Min Typ Max 10 — 100 10 — 40 300 — 1025 1 — — 15 –67108862 — 67108862 1 — 67108863 48.5 50 51.5 Freescale Semiconductor Unit T CKIL V V Unit MHz MHz MHz — — — — % ...
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... Table 33 demonstrates several examples of clock frequency settings. emi_slow_clk (MHz) nfc_podf (Division Factor) 100 (Boot mode) i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Test Conditions/Remarks — — — FPL mode, integer and fractional 300 MHz @ avdd = 1 ...
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... Setting the rhoh > also recommended that the rhoh (RE_B high to output high-Z). In most devices, the rhz NF1 NF3 NF5 NF8 NF9 command Figure 10. Command Latch Cycle Timing T-Clock Period (ns) 33. 44.33 22 NF2 NF4 Freescale Semiconductor ...
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... NFWE_B NFALE NFIO[7:0] NFCE_B NFWE_B NFIO[15:0] NFCE_B NFRE_B NFRB_B NFIO[15:0] Figure 13. Read Data Latch Timing, Asymmetric Mode i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor NF4 NF3 NF10 NF11 NF5 NF7 NF6 NF8 NF9 Address Figure 11. Address Latch Cycle Timing ...
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... NFCE_B NFRE_B NFRB_B NF12 NFIO[15:0] Figure 14. Read Data Latch Timing, Symmetric Mode NFCLE NFCE_B NFWE_B NFRE_B NFRB_B i.MX53xA Automotive and Infotainment Applications Processors, Rev NF14 NF15 NF13 NF16 Data from NF NF19 NF20 NF21 NF22 Figure 15. Other Timing Parameters NF18 Freescale Semiconductor ...
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... MHz). 3 NF17 is defined only in asymmetric operation mode. NF17 max value is equivalent to max “emi_slow_clk” of the system. aclk i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Table 34. NFC—Timing Characteristics Symbol Asymmetric Mode Min 0.1 CLS t T – ...
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... Reference Manual External Signals and Pin Multiplexing Chapter, and IOMUXC Controller Chapter Nomenclature EIM_BCLK EIM_CSx EIM_RW EIM_OE EIM_EBx EIM_LBA EIM_A[25:16], EIM_DA[15:0] EIM_DAx (Addr/Data muxed mode) EIM_NFC_D (Data bus shared with NAND Flash) EIM_Dx (dedicated data bus) EIM_WAIT ) is Data propogation delay from I/O pad to Dpd Freescale Semiconductor ...
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... Setup MUM = 0, DSZ = 111 A[15:0] A[25:16] D[7:0], EIM_EB0 D[15:8], EIM_EB1 D[23:16], EIM_EB2 D[31:24], EIM_EB3 i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Table 36. EIM Internal Module Multiplexing Non Multiplexed Address/Data Mode 8 Bit 16 Bit MUM = 0, DSZ = 010 EIM_DA[15:0] EIM_DA[15:0] EIM_A[25:16] EIM_A[25:16] — ...
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... Address/Data mode 32 Bit 16 Bit 32 Bit MUM = 0, MUM = 1, MUM = 1, DSZ = 011 DSZ = 00 DSZ = 011 1 EIM_DA[15: EIM_DA[1 EIM_DA[15 0] 5:0] :0] EIM_A[24:1 EIM_A[ :16] NANDF_D[ 1 8:0] NANDF_D[ EIM_DA[7 EIM_DA[7: 7:0] :0] 0] NANDF_D[ EIM_DA[1 EIM_DA[15 15:8] 5:8] :8] EIM_D[23:1 — NANDF_D[ 6] 7:0] EIM_D[31:2 — NANDF_D[ 4] 15:8] Freescale Semiconductor ...
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... ID Parameter Min 2 WE1 BCLK Cycle time t WE2 BCLK Low Level 0.4*t Width i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor specify the timings related to the EIM module. All EIM output control WE2 WE1 WE4 WE6 WE8 WE10 WE12 WE14 WE16 Figure 16 ...
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... Freescale Semiconductor Max — — — — ...
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... BCLK ADDR Last Valid Address CSx_B WE_B ADV_B OE_B BEy_B DATA Figure 18. Synchronous Memory Read Access, WSC=1 i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor ≤ 104 MHz. If BCD = 1, then 133 MHz is WE4 Address v1 WE6 WE14 WE15 WE10 WE12 WE18 ...
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... Automotive and Infotainment Applications Processors, Rev WE4 Address V1 WE6 WE8 WE14 WE15 WE12 WE16 WE16 WE5 WE4 Address V1 Last WE6 WE8 WE15 WE14 WE10 ADH=1 NOTE WE5 WE7 WE9 WE13 WE17 D(V1) WE17 Write Data WE7 WE9 WE11 Freescale Semiconductor ...
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... Asynchronous read & write access length in cycles may vary from what is shown in Figure 25 as RWSC, OEN & CSN is configured differently. See i.MX53xA RM for the EIM program- ming model. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor WE4 WE5 Address V1 WE6 ...
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... Automotive and Infotainment Applications Processors, Rev start of access WE31 Address V1 WE39 WE35 WE37 D(V1) WE43 MAXDI start of access MAXDI WE31 Addr. V1 WE32A WE40A WE39 WE35A WE37 end of access WE32 Next Address WE40 WE36 WE38 WE44 end of access D(V1) WE44 WE36 WE38 Freescale Semiconductor ...
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... Figure 24. Asynchronous Memory Write Access (RWSC = 5, OEN=CSN=0) CSx_B ADDR/ M_DATA WE_B ADV_B OE_B BEy_B Figure 25. Asynchronous A/D Muxed Write Access (RWSC = 5, OEN=CSN=0) i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor WE31 Address V1 WE33 WE39 WE45 D(V1) WE41 WE41 WE31 D(V1) Addr ...
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... Next Address WE40 WE36 WE38 WE44 WE48 Max (If 133 Mhz is Min supported by SOC) — CSA — CSN -3 + (ADVN + — ADVA + 1 - CSA) — (WEA - CSA) — (WEN_CSN) — (OEA - CSA (OEA + 3 + (OEA + RADVN+RADVA RADVN+RADVA+A +ADH+1-CSA) DH+1-CSA) — (OEN - CSN) Freescale Semiconductor Unit ...
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... WE45 CSx_B Valid to BEy_B Valid (Write access) WE46 BEy_B Invalid to CSx_B Invalid (Write access) i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Determination by Synchronous measured 12 parameters WE12 - WE6 + (RBEA - CSA) WE7 - WE13 + (RBEN - CSN) WE14 - WE6 + (ADVA - CSA) WE7 - WE15 - CSN ...
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... The LPDDR2 interface fully complies with JESD209-2B, supporting LPDDR2-800. i.MX53xA Automotive and Infotainment Applications Processors, Rev Determination by Synchronous measured Min 12 parameters MAXCO - MAXCSO + MAXCO - MAXDTI MAXCSO + MAXDTI 0 Table 38 Max (If 133 Mhz is Unit supported by SOC) — — — — — ns Freescale Semiconductor ...
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... Figure 27. DDR SDRAM Basic Timing Parameters Figure 28 shows the write timing parameters. SDCLK SDCLK_B DDR21 DQS (output) DDR17 DQ (output) DQM (output) DDR17 i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor DDR4 DDR5 DDR4 DDR5 DDR4 DDR7 COL/BA DDR22 DDR18 DDR17 Data ...
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... NOTE DATA DATA DATA DATA DDR26 Table 40. CSPI Nomenclature and Routing GPIO, KPP, DISP0_DAT, CSI0_DAT and EIM_D through IOMUXC DISP0_DAT, CSI0_DAT and EIM through IOMUXC DISP0_DAT, EIM_A/D, SD1 and SD2 through IOMUXC DATA DATA DATA DATA Table 40. I/O Access Freescale Semiconductor ...
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... MISO Hold Time 2 CS10 RDY to SSx Time 1 See specific I/O AC parameters Section 4.5, “I SPI_RDY is sampled internally by ipg_clk and is asynchronous to all other CSPI signals. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Table 41 CS2 CS3 CS2 CS3 Symbol t clk t SW ...
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... LOAD PDmiso Table 43 lists the ECSPI master mode timing Symbol t clk RISE/FALL t CSLH CS5 CS6 CS4 Min Max Unit 100 — ns — ns — ns — ns — ns — ns — Min Max Unit 30 — — — — ns Half SCLK period — ns Freescale Semiconductor ...
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... The ESAI consists of independent transmitter and receiver sections, each section with its own clock generator. Table 45 shows the interface timing values. The number field in the table refers to timing signals found in Figure 32 and Figure 33. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Symbol t SCS t HCS = 20 pF) t LOAD PDmosi ...
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... Freescale Semiconductor 4 Unit ...
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... Periodically sampled and not 100% tested. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 1 2,3 ’ Symbol Expression — ...
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... Electrical Characteristics 63 SCKT (Input/Output) FST (Bit) Out FST (Word) Out Data Out FST (Bit) In FST (Word) In i.MX53xA Automotive and Infotainment Applications Processors, Rev First Bit Figure 32. ESAI Transmitter Timing 83 87 Last Bit 91 Freescale Semiconductor ...
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... SCKR (Input/Output) FSR (Bit) Out FSR (Word) Out Data In FSR (Bit) In FSR (Word) In i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor First Bit Figure 33. ESAI Receiver Timing Electrical Characteristics 70 72 Last Bit 75 71 ...
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... SCK SD3 CMD SD6 DAT0 DAT1 ...... DAT7 SD7 SD8 CMD DAT0 DAT1 ...... DAT7 Figure 34. SD/eMMC4.3 Timing Card Input Clock SD1 Symbols Min Max 400 25/ 20/ 100 400 — — — 3 TLH t — 3 THL t – Freescale Semiconductor Unit kHz MHz MHz kHz ...
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... Clock Frequency (MMC Full Speed/High Speed) eSDHC Output / Card Inputs CMD, DAT (Reference to CLK) SD2 eSDHC Output Delay eSDHC Input / Card Outputs CMD, DAT (Reference to CLK) i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor – 50 MHz. – 52 MHz. Table 47 lists the eMMC4.4 timing characteristics. Be aware ...
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... Automotive and Infotainment Applications Processors, Rev Symbols t ISU t IH Table 48 lists the MII receive channel signal timing Table 48. MII Receive Signal Timing 1 2 Min Max Unit 2.5 — ns 2.5 — ns Min Max Unit 5 — — ns 35% 65% FEC_RX_CLK period 35% 65% FEC_RX_CLK period Freescale Semiconductor ...
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... FEC_TX_CLK pulse width high M8 FEC_TX_CLK pulse width low 1 FEC_TX_EN, FEC_TX_CLK, and FEC_TXD0 have the same timing in 10 Mbps 7-wire interface mode. 2 Test conditions: 25pF on each output signal. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Figure 37 Table 49. Table 49. MII Transmit Signal Timing ...
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... Table 50. MII Async Inputs Signal Timing 1 M9 Figure 38. MII Async Inputs Timing Diagram Figure 39 Table 51. MII Transmit Signal Timing 1 Characteristics M8 Figure 38 shows MII asynchronous Min Max Unit 1.5 — FEC_TX_CLK period shows MII serial management channel Min Max Unit 0 — ns — — ns Freescale Semiconductor ...
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... The RMII mode timings are shown in No. M16 REF_CLK(FEC_TX_CLK) pulse width high M17 REF_CLK(FEC_TX_CLK) pulse width low M18 REF_CLK to FEC_TXD[1:0], FEC_TX_EN invalid M19 REF_CLK to FEC_TXD[1:0], FEC_TX_EN valid i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 1 Characteristics M14 M12 M13 Table 52 and Figure 40. Table 52. RMII Signal Timing ...
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... Tx and Rx pins; these ports are named TXCAN and RXCAN, respectively. i.MX53xA Automotive and Infotainment Applications Processors, Rev Table 52. RMII Signal Timing (continued) 1 Characteristics M16 M18 M19 M20 M21 Min Max Unit 4 — — ns M17 Freescale Semiconductor ...
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... If such a device does stretch the LOW period of the I2CLK signal, it must output the next data bit to the I2DAT line max_rise_time (IC9) + data_setup_time (IC7) = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification) before the I2CLK line is released total capacitance of one bus line in pF. b i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 2 C module module timing characteristics. IC11 IC10 IC7 ...
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... Y[1] Y[1] G[5] Y[2] Y[2] R[0] Y[3] Y[3] R[1] Y[4] Y[4] R[2] Y[5] Y[5] R[3] Y[6] Y[6] R[4] Y[7] Y[7] Freescale Semiconductor 7 C[0] C[1] C[2] C[3] C[4] C[5] C[6] C[7] C[8] C[9] Y[0] Y[1] Y[2] Y[3] Y[4] Y[5] Y[6] Y[7] Y[8] ...
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... Then SENSB_HSYNC goes to high and hold for the entire line. Pixel clock is valid as long as SENSB_HSYNC is high. Data is latched at the rising edge of the valid pixel clocks. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Active Line n+1th frame invalid ...
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... Automotive and Infotainment Applications Processors, Rev Section 4.7.8.2.2, “Gated Clock n+1th frame 1st byte is that of a typical sensor. Some other sensors may have a slightly IP2 IP3 Figure 44. Sensor Interface Timing Diagram Figure 43). All incoming pixel clocks are invalid 1st byte 1/IP1 Freescale Semiconductor Mode,”) ...
Page 83
... Data and control holdup time 4.7.8.4 IPU Display Interface Signal Mapping The IPU supports a number of display output video formats. Interface Pins used during various supported video interface formats. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Electrical Characteristics Symbol Min Fpck 0.01 ...
Page 84
... Groups should not be overlapped. DAT[3] b) The bit order is expressed in DAT[4] each of the bit groups, for example B[0] = least significant blue pixel DAT[5] bit DAT[6] DAT[7] DAT[8] DAT[9] DAT[10] DAT[11] DAT[12] DAT[13] DAT[14] DAT[15] — — — — — — Freescale Semiconductor ...
Page 85
... This mode works in compliance with recommendation ITU-R BT.656. The timing reference signals (frame start, frame end, line start, and line end) are embedded in the 8-bit data bus. Only video data is supported, transmission of non-video related data during blanking intervals is not supported. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor LCD 18-bit 24 Bit ...
Page 86
... When a DI decides to put a new asynchronous data in the bus, a new internal start (local start point) is generated. The signals generators calculate predefined UP and DOWN values to change pins states with half DI_CLK resolution. i.MX53xA Automotive and Infotainment Applications Processors, Rev NOTE NOTE Freescale Semiconductor ...
Page 87
... VSYNC HSYNC LINE 1 HSYNC DRDY IPP_DISP_CLK IPP_DATA Figure 45. Interface Timing Diagram for TFT (Active Matrix) Panels i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor LINE 2 LINE 3 LINE Electrical Characteristics LINE n-1 LINE n m– ...
Page 88
... All parameters shown in the figure are programmable. IP13 VSYNC HSYNC DRDY IP11 Figure 47. TFT Panels Timing Diagram—Vertical Sync Pulse i.MX53xA Automotive and Infotainment Applications Processors, Rev IP8o IP8 D0 IP9o IP9 IP6 Start of frame IP14 IP12 IP7 IP5 Dn D1 IP10 End of frame IP15 Freescale Semiconductor ...
Page 89
... IP10 Horizontal blank interval 2 IP12 Screen height IP13 VSYNC width IP14 Vertical blank interval 1 IP15 Vertical blank interval 2 i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Figure 46 Symbol Value 1 Tdicp ( ) Display interface clock. Tdpcp DISP_CLK_PER_PIXEL Time of translation of one pixel to display, × ...
Page 90
... DI’s counter. DRDY_OFFSET—offset of DRDY edges from a suitable local start point, when a corresponding data has been set on the × bus, in DI_CLK 2 (0.5 DI_CLK Resolution) The DRDY_OFFSET should be built by suitable DI’s counter. for integer DISP_CLK_PERIOD --------------------------------------------------- - DI_CLK_PERIOD for fractional DISP_CLK_PERIOD --------------------------------------------------- - DI_CLK_PERIOD Freescale Semiconductor Unit ...
Page 91
... The exact conditions have not been finalized, but will likely match the current customer requirement for their specific display. These conditions may be chip specific. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor ± Accuracy = T diclk 0.62ns ...
Page 92
... The active intervals—during which data is transferred—are marked by the HSYNC signal being high. i.MX53xA Automotive and Infotainment Applications Processors, Rev × ⎛ 2 DISP_CLK_DOWN 1 × ---------------------------------------------------------- - Tdicd = -- - T diclk ceil ⎝ DI_CLK_PERIOD 2 × ⎛ 2 DISP_CLK_UP 1 × ----------------------------------------------- - Tdicu = -- - T diclk ceil ⎝ DI_CLK_PERIOD 2 49. NOTE ⎞ ⎠ ⎞ ⎠ Freescale Semiconductor ...
Page 93
... VSYNC 621 622 HSYNC DRDY VSYNC Even Field 308 309 HSYNC DRDY VSYNC Odd Field Figure 49. TV Encoder Interface Timing Diagram i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Pixel Data Timing 524 525 Even Field 262 263 264 265 ...
Page 94
... Degrees — 75 — dB — 0.8 — ±Degrees — 1.5 — ±% — –70 — dB — –47 — dB — 0.5 — ±Degrees — 2.5 — ±% — 0.1 — ±% — 1.0 — ±% Freescale Semiconductor ...
Page 95
... A pause between two different display accesses can be guaranteed by programing suitable access sizes. There are no minimal/maximal hold/setup times hard defined by DI. Each control signal can be switched at any time during access size. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Conditions — 2 ...
Page 96
... Single access mode (all control signals are not active for one display interface clock after each display access) Figure 50. Asynchronous Parallel System 80 Interface (Type 1) Timing Diagram i.MX53xA Automotive and Infotainment Applications Processors, Rev Burst access mode with sampling by CS signal Freescale Semiconductor ...
Page 97
... Burst access mode with sampling by WR/RD signals IPP_CS IPP_DATA Single access mode (all control signals are not active for one display interface clock after each display access) Figure 51. Asynchronous Parallel System 80 Interface (Type 2) Timing Diagram i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Electrical Characteristics 97 ...
Page 98
... Single access mode (all control signals are not active for one display interface clock after each display access) Figure 52. Asynchronous Parallel System 68k Interface (Type 1) Timing Diagram i.MX53xA Automotive and Infotainment Applications Processors, Rev Burst access mode with sampling by CS signal Freescale Semiconductor ...
Page 99
... DI_CLK delay. The DI finishes a current access and a next access is postponed until IPP_WAIT release. Figure 54 shows timing of the parallel interface with IPP_WAIT control. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Burst access mode with sampling by ENABLE signal Electrical Characteristics 99 ...
Page 100
... Table 61 shows timing characteristics at display access level. All timing diagrams are based on active low control signals (signals polarity is controlled through the DI_DISP_SIG_POL register). i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 100 waiting waiting Freescale Semiconductor ...
Page 101
... Address Write system cycle time Tcycwa IP28d Data Write system cycle time IP29 RS start IP30 CS start IP31 CS hold IP32 RS hold IP33 Read start i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor IP36 IP34 D1 IP28d Symbol Value Tcycr ACCESS_SIZE_# ACCESS_SIZE_# Tcycwd ACCESS_SIZE_# Tdcsrr UP# ...
Page 102
... Point of input data sampling by DI, predefined in DC Microcode 1 Max Tdicpr+1.24 Tdicpw+1.24 Tdicurs+1.24 Tdicucs+1.24 5 Tdicdcs – Tdicucs+1.24 7 Tdicdrs – Tdicurs+1.24 Tdicur+1.24 9 Tdicdr – Tdicur+1.24 Tdicuw+1.24 11 Tdicdw–Tdicuw+1. Tdrp – Tlbd –Tdicur–1. 24 Tdicpr – Tdicdr – 1.24 Freescale Semiconductor Unit — Unit ...
Page 103
... DISP_UP is predefined in REGISTER. 6 Display control down for RS DISP_DOWN is predefined in REGISTER. 7 Display control up for RS DISP_UP is predefined in REGISTER. 8 Display control down for read DISP_DOWN is predefined in REGISTER. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Min — Tdrp – 1.24 Tdrp DI_ACCESS_SIZE_# × ---------------------------------------------------- - Tdicpr = T DI_CLK ...
Page 104
... DISP_UP_# 1 × --------------------------------------------- - Tdicur = -- - T DI_CLK ceil ⎝ DI_CLK_PERIOD 2 × ⎛ 2 DISP_DOWN_# 1 × ------------------------------------------------- - = -- - T DI_CLK ceil ⎝ DI_CLK_PERIOD 2 × ⎛ 2 DISP_UP_# 1 × --------------------------------------------- - Tdicuw = -- - T DI_CLK ceil ⎝ DI_CLK_PERIOD 2 DISP#_READ_EN × --------------------------------------------- - Tdrp = T DI_CLK ceil DI_CLK_PERIOD ⎞ ⎠ ⎞ ⎠ ⎞ ⎠ Freescale Semiconductor ...
Page 105
... DISPB_D#_CS delay DISPB_SD_D_CLK DISPB_SD_D (Output) DISPB_SD_D (Input) programed DISPB_D#_CS delay DISPB_SD_D_CLK DISPB_SD_D (Output) DISPB_SD_D (Input) Figure 57. 4-Wire Serial Interface Timing Diagram i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Preamble Write Preamble Read RW RS Preamble D7 Electrical Characteristics programed delay ...
Page 106
... DISPB_SD_D_CLK DISPB_SD_D (Output) DISPB_SD_D (Input) programed DISPB_SER_RS delay Figure 58. 5-Wire Serial Interface Timing Diagram i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 106 Write programed delay RW D7 Preamble Read programed delay RW Preamble D7 programed delay Output data programed delay Input data Freescale Semiconductor ...
Page 107
... IP48 Read system cycle time IP49 Write system cycle time IP50 Read clock low pulse width IP51 Read clock high pulse width Trh i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Table 62 shows timing characteristics at display access IP73 IP72 IP71 ...
Page 108
... Tdicpr – Tdicdr – 1.24 Tdicdw — Tdicpw – Tdicdw — Tdicpr Tdicpr+1.24 Tdicpw Tdicpw+1.24 Tdicdr Tdicdr+1.24 Tdicur Tdicur+1.24 Tdicdw Tdicdw+1.24 Tdicuw Tdicuw+1.24 Tdrp Tdrp+1.24 Toclk Toclk+1.24 Tdicurs Tdicurs+1.24 Tdicdrs Tdicdrs+1.24 Tdicucs Tdicucs+1.24 Tdicdcs Tdicdcs+1.24 Freescale Semiconductor Unit ...
Page 109
... Display interface clock offset value CLK_OFFSET is predefined in REGISTER. 12 Display RS up time DISP_RS_UP is predefined in REGISTER. 13 Display RS down time DISP_RS_DOWN is predefined in REGISTER. 14 Display RS up time DISP_CS_UP is predefined in REGISTER. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor × ⎛ 2 DISP_DOWN_# 1 × ------------------------------------------------- - Tdicdr = -- - T DI_CLK ceil ⎝ ...
Page 110
... Figure 61 show the timing of MediaLB Controller, and MediaLB controller timing characteristics. Figure 61. MediaLB Pulse Width Variation Timing i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 110 DISP_CS_DOWN_# × -------------------------------------------------- - Tdicdcs = T DI_CLK ceil DI_CLK_PERIOD Figure 60. MediaLB Timing Table 63 and Table 64 lists the Freescale Semiconductor ...
Page 111
... Therefore, coupling must be minimized while meeting the maximum capacitive load listed. Ground = 0.0 V; load capacitance = 40 pF; MediaLB speed = 1024 Fs kHz; all timing parameters specified from the valid voltage threshold as listed in i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Min Typ Max 11 ...
Page 112
... Min: 1024*fs at 44.0 kHz Typ: 1024*fs at 48.0 kHz Max: 1024fs*fs at 48.1 kHz Max: 1024*fs PLL unlocked — ns — — ns PLL unlocked — ns — PLL unlocked ns pp Note — ns — — ns — ns — — ns Note One Wire Device Tx “Presence Pulse” OW4 Freescale Semiconductor ...
Page 113
... OW6 Transmission Time Slot Recovery time Figure 64 depicts Write 1 Sequence timing, lists the timing parameters. One-Wire bus (BATT_LINE) OW7 Figure 64. Write 1 Sequence Timing Diagram i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Symbol Min t 480 RSTL t 15 PDH t 60 PDL ...
Page 114
... Figure 65. Read Sequence Timing Diagram Table 67. WR1 /RD Timing Parameters Symbol t LOW1 t SLOT LOWR t RDV t RELEASE Table 68 lists the PWM timing parameters Figure 66. PWM Timing Min Typ Max 117 120 — — — 15 — 0 — Freescale Semiconductor Unit µs µs µs µs µs µs ...
Page 115
... Host interface signal capacitance at the host connector 1 SRISE and SFALL shall meet this requirement when measured at the sender’s connector from 10–90% of full signal amplitude with all capacitive loads from 15 i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Table 68. PWM Output Timing Parameter Min 1 12.29 9.91 — ...
Page 116
... Table 70. PATA Timing Parameters Description UDMA2, UDMA3 UDMA0, UDMA1, UDMA2, UDMA3, UDMA4 Value/ 1 Contributing Factor Peripheral clock frequency (7.5 ns for 133 MHz clock) UDMA0 15 ns UDMA1 UDMA4 5 ns UDMA5 4 ns 5.0 ns UDMA5 4.6 ns 12.0 ns 8.5 ns 8 Transceiver Transceiver Freescale Semiconductor ...
Page 117
... T > tsu + thi + tskew3 + tskew4 t0 — t0(min) = (time_1 + time_2r+ time_9 i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Description Table 71 lists the timing parameters for PIO read. Figure 68. PIO Read Timing Diagram Table 71. PIO Read Timing Parameters ...
Page 118
... Automotive and Infotainment Applications Processors, Rev. 1 118 Table 72 lists the timing parameters for PIO write. Figure 69. Multi-word DMA (MDMA) Timing Table 72. PIO Write Timing Parameters Value Controlling Variable time_1 time_2w time_9 If not met, increase time_2w time_4 time_ax time_1, time_2r, time_9 — — Freescale Semiconductor ...
Page 119
... T – (tskew1 + tskew2 + tskew6) tL — tL (max) = (time_d + time_k – 2) i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Figure 71 shows timing for MDMA write, and Figure 70. MDMA Read Timing Diagram Figure 71. MDMA Write Timing Diagram Value × ...
Page 120
... Automotive and Infotainment Applications Processors, Rev. 1 120 Value × T – tskew1 × T – tskew1 and Figure 71) equals (tk – 2*T). Figure 73 shows timing when the UDMA in device terminates transfer, and Controlling Variable time_jn — shows timing when the UDMA in Freescale Semiconductor ...
Page 121
... Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Table 74. UDMA in Burst Timing Parameters Description × T) – (tskew1 + tskew2) × T) – (tskew1 + tskew2) × ...
Page 122
... T) – (tskew1 + tskew2) × T – tskew1 × T – tskew1 Figure 76 shows timing when the UDMA out device terminates transfer, and Controlling Variable T big enough time_rp tcable2) > trfs (drive) time_rp time_mlix time_zah time_dzfs time_cvh — shows timing when the UDMA out Freescale Semiconductor ...
Page 123
... Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Value × T) – (tskew1 + tskew2) × T) – (tskew1 + tskew2) × (tskew1 + tskew2) × T) – (tskew1 + tskew2) × T) – (tskew1 + tskew2) × ...
Page 124
... Test Conditions — — For information about total phase jitter, see following section — — Controlling Variable — time_dzfs time_ss T – (tskew1 + tskew2) — — — — time_cvh — Min Max 350 850 175 2,000 — 156.25 Freescale Semiconductor Unit RMS % UI MHz ...
Page 125
... Table 77 provides specifications for SATA PHY transmitter characteristics. Table 77. SATA2 PHY Transmitter Characteristics Parameters Transmit common mode voltage Transmitter pre-emphasis accuracy (measured change in de-emphasized bit) i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor NOTE Symbol Min V 0.4 CTM — –0.5 ...
Page 126
... MHz to 156.25 MHz. SATA_REXT does not need to be connected, as the termination impedance is not of consequence. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 126 Symbol Min — MIN_RX_EYE_HEIGHT PPM –400 NOTE Typ Max Unit — 175 mV — 400 ppm Ω. 1% precision resistor Freescale Semiconductor ...
Page 127
... Data Inputs Data Outputs Data Outputs Data Outputs Figure 80. Boundary Scan (JTAG) Timing Diagram i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Figure 80 depicts the SJC boundary scan timing. SJ1 SJ2 VM VIH VIL Figure 79. Test Clock Input Timing Diagram SJ4 ...
Page 128
... Input Data Valid SJ10 Output Data Valid SJ11 SJ10 Output Data Valid SJ13 Figure 82. TRST Timing Diagram Table 79. JTAG Timing 1,2 Parameter VIH SJ9 All Frequencies Unit Min Max 0.001 22 MHz 45 — ns 22.5 — ns — — — ns — — — ns Freescale Semiconductor ...
Page 129
... Modulating Rx clock (SRCK) period SRCK high period SRCK low period Modulating Tx clock (STCLK) period STCLK high period STCLK low period i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Table 79. JTAG Timing (continued) 1,2 Parameter Table 80. SPDIF Timing Parameters Symbol — ...
Page 130
... Type and Access SSI 1 Internal SSI 2 Internal AUD3 External – AUD3 I/O AUD4 External – EIM or CSPI1 I/O through IOMUXC AUD5 External – EIM or SD1 I/O through IOMUXC AUD6 External – EIM or DISP2 through IOMUXC SSI 3 Internal NOTE M M Freescale Semiconductor ...
Page 131
... SS12 (Tx) CK high to FS (wl) low SS14 (Tx/Rx) Internal FS rise time SS15 (Tx/Rx) Internal FS fall time SS16 (Tx) CK high to STXD valid from high impedance i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Table 82 SS1 SS5 SS4 SS8 SS10 SS14 SS16 SS17 ...
Page 132
... Tx Data (for example, during AC97 mode of operation). i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 132 Parameter Synchronous Internal Clock Operation NOTE Min Max Unit — 15.0 ns — 15.0 ns — 6.0 ns 10.0 — ns 0.0 — ns — 25.0 pF Freescale Semiconductor ...
Page 133
... SS11 (Rx) CK high to FS (wl) high SS13 (Rx) CK high to FS (wl) low SS20 SRXD setup time before (Rx) CK low SS21 SRXD hold time after (Rx) CK low i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Table 83 SS1 SS5 SS4 SS9 SS11 SS20 SS51 ...
Page 134
... For internal Frame Sync operation using external clock, the FS timing is same as that of Tx Data (for example, during AC97 mode of operation). i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 134 Parameter Oversampling Clock Operation NOTE Min Max Unit 15.04 — ns 6.0 — ns — 3.0 ns 6.0 — ns — 3.0 ns Freescale Semiconductor ...
Page 135
... SS31 (Tx) CK high to FS (wl) high SS33 (Tx) CK high to FS (wl) low SS37 (Tx) CK high to STXD valid from high impedance SS38 (Tx) CK high to STXD high/low i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Table 84 SS22 SS25 SS26 SS27 SS29 SS31 SS37 SS44 ...
Page 136
... For internal Frame Sync operation using external clock, the FS timing is same as that of Tx Data (for example, during AC97 mode of operation). i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 136 Parameter Synchronous External Clock Operation NOTE Min Max Unit — 15.0 ns 10.0 — ns 2.0 — ns — 6.0 ns Freescale Semiconductor ...
Page 137
... SS35 (Tx/Rx) External FS rise time SS36 (Tx/Rx) External FS fall time SS40 SRXD setup time before (Rx) CK low SS41 SRXD hold time after (Rx) CK low i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Table 85 SS22 SS26 SS25 SS28 SS30 SS32 SS35 ...
Page 138
... Input RTS from DTE to DCE Output CTS from DCE to DTE Input DTR from DTE to DCE Output DSR from DCE to DTE DCD from DCE to DTE RING from DCE to DTE Serial data from DCE to DTE Input Serial data from DTE to DCE Freescale Semiconductor ...
Page 139
... The UART receiver can tolerate 1/(16*F exceed 3/(16*F ). baud_rate Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16. baud_rate i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor UA1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Symbol t 1/F Tbit ...
Page 140
... Table 90 UA6 UA5 UA5 Possible Bit 5 Bit 6 Bit 7 Parity Bit Min Max 2 1/F – 1/F + baud_rate baud_rate ) 1/(16*F ) baud_rate baud_rate 1.41 us (5/16)*(1/F baud_rate Freescale Semiconductor lists STOP BIT Units — — lists the STOP BIT Units — ) — ...
Page 141
... Transmit USB_TXOE_B USB_DAT_VP USB_SE0_VM Figure 93. USB Transmit Waveform in DAT_SE0 Bidirectional Mode i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor ) tolerance in each bit. But accumulation tolerance in one frame must not baud_rate Parameters.” Direction Transmit enable, active low TX data when USB_TXOE_B is low ...
Page 142
... RX Rise/Fall Time USB_SE0_VM i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 142 US7 Signal Name Direction Min USB_DAT_VP Out -— Out — Out — USB_DAT_VP Out 49.0 USB_DAT_VP In — In — US8 Conditions / Max Unit Reference Signal 51.0 % — Freescale Semiconductor ...
Page 143
... USB_SE0_VM USB_VP1 USB_VM1 Transmit USB_TXOE_B USB_DAT_VP USB_SE0_VM Figure 95. USB Transmit Waveform in DAT_SE0 Unidirectional Mode i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Direction Out Transmit enable, active low Out TX data when USB_TXOE_B is low Out SE0 drive when USB_TXOE_B is low In Buffered data on DP when USB_TXOE_B is high ...
Page 144
... RX Rise/Fall Time US16 RX Rise/Fall Time i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 144 US15 Signal Min Source Out — Out — Out — Out 49.0 USB_VP1 In — USB_VM1 In — US16 Condition / Max Unit Reference Signal 51.0 % — Freescale Semiconductor ...
Page 145
... US21 Figure 97. USB Transmit Waveform in VP_VM Bidirectional Mode Receive USB_DAT_VP USB_SE0_VM Figure 98. USB Receive Waveform in VP_VM Bidirectional Mode i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Direction Out Transmit enable, active low Out (Tx data when USB_TXOE_B is low In (Rx data when USB_TXOE_B is high ...
Page 146
... Signal Name Direction Min USB_DAT_V Out — P USB_SE0_V Out — M USB_TXOE Out — _B USB_DAT_V Out 49.0 P USB_SE0_V Out -3.0 M USB_DAT_V In — P USB_SE0_V In — M USB_DAT_V In -4.0 P Condition / Max Unit Reference Signal 51.0 % — +3.0 ns USB_DAT_VP 3 3 +4.0 ns USB_SE0_VM Freescale Semiconductor ...
Page 147
... USB_VP1 USB_VM1 Transmit USB_TXOE_B USB_DAT_VP USB_SE0_VM US33 Figure 99. USB Transmit Waveform in VP_VM Unidirectional Mode i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Direction Out Transmit enable, active low Out TX VP data when USB_TXOE_B is low Out TX VM data when USB_TXOE_B is low In ...
Page 148
... US40 US39 Signal Direction Min USB_DAT_VP Out — USB_SE0_V Out — M USB_TXOE_ Out — B USB_DAT_VP Out 49.0 USB_SE0_V Out -3.0 M USB_VP1 In — USB_VM1 In — USB_VP1 In -4.0 Conditions / Max Unit Reference Signal 51.0 % — 3.0 ns USB_DAT_VP 3 3 +4.0 ns USB_VM1 Freescale Semiconductor ...
Page 149
... USB PHY AC Parameters Table 101 lists the AC timing parameters for USB PHY. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Direction In Interface clock. All interface signals are synchronous to Clock. Bi-directional data bus, driven low by the link during idle. Bus I/O ownership is determined by Dir ...
Page 150
... MHz All conditions Min Typ –150 — Max 300 20 300 0.2 Min Typ Max –0.05 — 0.5 0.8 2.5 1.3 — 2 1.3 2 – – – – Max — 150 — 200 — 50 — 100 — 60 Freescale Semiconductor Unit Unit Unit ppm ...
Page 151
... Parameter Min Frequency 1 Recommended nominal frequency 32.768 kHz. Table 107 shows the CKIL electrical specifications. Parameter Min Frequency 16 i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor VBUS Table 104. Comparators Thresholds Conditions Min — 0.8 — 0.8 — 0.2 — ...
Page 152
... Automotive and Infotainment Applications Processors, Rev. 1 152 Symbol Min V 1.15 VID_DIG_PLL V 1.7 VDD_ANA_PLL — — — — — — — VID_DIG_PLL I VDD_ANA_PLL E-Fuse Name N/A Typ Max Units 1.2 1.3 V 1.8 1.95 V — +/–3 % –18 — dB –15 — dB — 125 mA Details Boot Mode selection Freescale Semiconductor ...
Page 153
... SPI CSPI EIM_A25, EIM_D21, EIM_D22, EIM_D28 SPI ECSPI-1 EIM_D[19:16] SPI ECSPI-2 CSI_DAT[10:8], EIM_LBA i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor E-Fuse Name BOOT_CFG1[7]/Test Mode Selection BOOT_CFG1[6]/Test Mode Selection BOOT_CFG1[5]/Test Mode Selection BOOT_CFG1[4] BOOT_CFG1[3] BOOT_CFG1[2] BOOT_CFG1[1] BOOT_CFG1[0] ...
Page 154
... NAND data can be muxed either over EIM data or PATA data • Only CS0 is supported bit bit bit bit — — — — — RXD/TXD only RXD/TXD only RXD/TXD only RXD/TXD only RXD/TXD only — 6), LDO output to VDD_DIG_PLL Freescale Semiconductor ...
Page 155
... Figure 102 shows the top view of the 19×19 mm package, location (529 solder balls) of the 19×19 mm package, and mm package. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Figure 103 Figure 104 Figure 102 Package Top View Package Information and Contact Assignments shows the bottom view and the ball shows the side view of the 19× ...
Page 156
... Package Information and Contact Assignments Figure 103 Package, 529 Solder Balls, Bottom View i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 156 Figure 104 Package Side View Freescale Semiconductor ...
Page 157
... U13 NVCC_LVDS_BG U14 NVCC_NANDF T12 NVCC_PATA N7 NVCC_RESET H16 NVCC_SD1 H15 i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Package Information and Contact Assignments 102, Figure 103, and Figure 104. Table 113 shows the package ball map. Package Pin Assignment(s) 157 ...
Page 158
... G10, G11, G8, H11, H7, H9, J10, J12, J8, K11, K7, K9, L10, L12, L8 VDD_REG G18 VP A15, B15 VPH A9, B9 Table 112 displays an alpha-sorted list of the signal assignments including power rails. The table also includes out of reset pad state. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 158 Package Pin Assignment(s) Freescale Semiconductor ...
Page 159
... R4 NVCC_CSI CSI0_DATA_E P3 NVCC_CSI N CSI0_MCLK P2 NVCC_CSI CSI0_PIXCLK P1 NVCC_CSI CSI0_VSYNC P4 NVCC_CSI i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Package Information and Contact Assignments Out of Reset Condition I/O Buffer Type Alt. Block I/O Mode LVIO ALT0 SRC src_BOOT_MOD E[0] LVIO ALT0 SRC ...
Page 160
... Input 100 KΩ PU Input 100 KΩ PU Input 100 KΩ PD Input 100 KΩ PU Input 100 KΩ PU Input 100 KΩ PU Input 100 KΩ PU Input 100 KΩ PD Input 100 KΩ PD Input 100 KΩ PD Input 100 KΩ PD Input 100 KΩ PD Input 100 KΩ PU Freescale Semiconductor ...
Page 161
... NVCC_EMI_DRAM RATION DRAM_CAS L18 NVCC_EMI_DRAM DRAM_CS0 K18 NVCC_EMI_DRAM DRAM_CS1 P19 NVCC_EMI_DRAM i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Package Information and Contact Assignments Out of Reset Condition I/O Buffer Type Alt. Block I/O Mode GPIO ALT1 GPIO-4 gpio4_GPIO[30] DDR3 ALT0 ...
Page 162
... Value Output High Output High Output High Output High Output High Output High Output High Output High Output High Output High Output High Output High Output High Output High Output High Output High Output High Output High Output High Freescale Semiconductor ...
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... NVCC_EMI_DRAM DRAM_RESE P18 NVCC_EMI_DRAM T DRAM_SDBA R19 NVCC_EMI_DRAM 0 DRAM_SDBA P20 NVCC_EMI_DRAM 1 i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Package Information and Contact Assignments Out of Reset Condition I/O Buffer Type Alt. Block I/O Mode DDR3 ALT0 EXTMC emi_DRAM_D[26 ] DDR3 ALT0 EXTMC emi_DRAM_D[27 ...
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... Directio Config./ n Value Output Low Output Low Output Low Output Floating Output Floating Output Floating Output Floating Output Low Output Low Input Low Input High Input Low Input High Input Low Input High Input Low Input High Output High Freescale Semiconductor ...
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... V5 NVCC_EIM_SEC EIM_D27 V4 NVCC_EIM_SEC EIM_D28 AA1 NVCC_EIM_SEC EIM_D29 AA2 NVCC_EIM_SEC i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Package Information and Contact Assignments Out of Reset Condition I/O Buffer Type Alt. Block I/O Mode ANALOG — SRTC ECKIL {no block I/O by this name ...
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... KΩ PU Input 100 KΩ PU Input 100 KΩ PU Input 100 KΩ PU Input 100 KΩ Input 100 KΩ Input 100 KΩ Input 100 KΩ Input 100 KΩ Input 100 KΩ Input 100 KΩ Input 100 KΩ Input 100 KΩ Output — Freescale Semiconductor ...
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... GPIO_10 W16 TVDAC_AHVDDRG B GPIO_11 V17 TVDAC_AHVDDRG B GPIO_12 W17 TVDAC_AHVDDRG B i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Package Information and Contact Assignments Out of Reset Condition I/O Buffer Type Alt. Block I/O Mode UHVIO ALT0 EXTMC emi_EIM_EB[1] UHVIO ALT1 GPIO-2 gpio2_GPIO[30] ...
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... KΩ PU Input 100 KΩ PD Input 47 KΩ PU Input Keeper Input 47 KΩ PU Input 47 KΩ Input 100 KΩ PU Input 100 KΩ PU Input 100 KΩ PU Input 100 KΩ PU Input 100 KΩ PU Input 360 KΩ PD Input 100 KΩ PU Input 100 KΩ PU Freescale Semiconductor ...
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... AC13 NVCC_LVDS N LVDS1_TX1_P AB13 NVCC_LVDS LVDS1_TX2_ AC12 NVCC_LVDS N LVDS1_TX2_P AB12 NVCC_LVDS i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Package Information and Contact Assignments Out of Reset Condition I/O Buffer Type Alt. Block I/O Mode UHVIO ALT1 GPIO-4 gpio4_GPIO[13] UHVIO ALT1 ...
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... Input 100 KΩ PU Input 100 KΩ PU Input 100 KΩ PU Input 100 KΩ PU Input 100 KΩ PU Input 100 KΩ PU Input 100 KΩ PU Input 100 KΩ PU Input 100 KΩ PU Input 100 KΩ PU Input 100 KΩ PU Input 100 KΩ PU Input 100 KΩ PU Freescale Semiconductor ...
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... A12 VPH SATA_RXP B12 VPH SATA_TXM B10 VPH SATA_TXP A10 VPH i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Package Information and Contact Assignments Out of Reset Condition I/O Buffer Type Alt. Block I/O Mode UHVIO ALT1 GPIO-2 gpio2_GPIO[2] UHVIO ALT1 ...
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... Input 100 KΩ PU Input 100 KΩ PU Input 100 KΩ PU Input 100 KΩ PU Input 100 KΩ PU Input 100 KΩ PU Input 100 KΩ PD — — — — — — — — — — — — — — — — — — Freescale Semiconductor ...
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... During power-on reset this port acts as output for diagnostic signal ANY_PU_RST KEY_COL0 and GPIO_19 act as output for diagnostic signals during power-on reset. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Package Information and Contact Assignments Out of Reset Condition I/O Buffer Type Alt ...
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... Package Information and Contact Assignments 6 mm, 0.8 Pitch Ball Map shows the 19 × 19 mm, 0.8 pitch ball map. Table 113 i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 174 Table 113. 19 × 19 mm, 0.8 Pitch Ball Map Freescale Semiconductor ...
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... Table 113. 19 × 19 mm, 0.8 Pitch Ball Map (continued) i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Package Information and Contact Assignments 175 ...
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... Package Information and Contact Assignments Table 113. 19 × 19 mm, 0.8 Pitch Ball Map (continued) i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 176 Freescale Semiconductor ...
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... Table 113. 19 × 19 mm, 0.8 Pitch Ball Map (continued) i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Package Information and Contact Assignments 177 ...
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... MHz from 1.0/1.05/1.1 to 1.05/1.1/1.15 V minimum/nominal/maximum. — Stop mode from 0.9/0.95/1.1 to 0.8/0.85/1.15 V minimum/nominal/maximum. • Added statements to footnotes 4 and 5. Rev 0 02/2011 Initial release. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 178 Substantive Change(s) Section 3.1, “Special Signal Considerations.” Table 6, "i.MX53xA Operating Ranges," on page 19. Freescale Semiconductor ...
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... THIS PAGE INTENTIONALLY LEFT BLANK i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 179 ...
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... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...