ADV7311KST Analog Devices Inc, ADV7311KST Datasheet - Page 36

• Manufacturer Part Number: ADV7311KST
• Description: IC VID ENC 6-12BIT DAC'S 64LQFP
• Manufacturer: Analog Devices Inc
• Type: Video Encoderr

Specifications of ADV7311KST

• Rohs Status: RoHS non-compliant
• Applications: DVD, SD/HD
• Voltage - Supply, Analog: 2.5V
• Voltage - Supply, Digital: 2.5V
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Input Format: Digital
• Output Format: Analog
• Supply Voltage Range: 2.375V To 2.625V
• Operating Temperature Range: 0°C To +70°C
• Tv / Video Case Style: LQFP
• No. Of Pins: 64
• Msl: MSL 1 - Unlimited
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADV7310/ADV7311
SD Real-Time Control, Subcarrier Reset, and Timing Reset
[Subaddress 44h, Bit 2, 1]
Together with the RTC_SCR_TR pin and SD Mode Register 3
[Address 44h, Bit 1, 2], the ADV7310/ADV7311 can be used in
(a) timing reset mode, (b) subcarrier phase reset mode, or (c)
RTC mode.
a. A timing reset is achieved in a low-to-high transition on the
b. In subcarrier phase reset, a low-to-high transition on the
RTC_SCR_TR pin (Pin 31). In this state, the horizontal and
vertical counters will remain reset. On releasing this pin (set
to low), the internal counters will commence counting again,
the field count will start on Field 1, and the subcarrier phase
will be reset.
The minimum time the pin has to be held high is one clock
cycle; otherwise, this reset signal might not be recognized.
This timing reset applies to the SD timing counters only.
RTC_SCR_TR pin (Pin 31) will reset the subcarrier phase to
zero on the field following the subcarrier phase reset when the
SD RTC/TR/SCR control bits at Address 44h are set to 01.
DISPLAY
307
NO TIMING RESET APPLIED
TIMING RESET APPLIED
NO F
F
SC
307
307
307
RESET APPLIED
SC
RESET APPLIED
DISPLAY
DISPLAY
DISPLAY
310
310
310
1
Figure 31. Subcarrier Reset Timing Diagram
START OF FIELD 1
Figure 30. Timing Reset Timing Diagram
2
3
313
313
313
4
START OF FIELD 4 OR 8
START OF FIELD 4 OR 8
START OF FIELD 4 OR 8
5
–36–
6
c. In RTC mode, the ADV7310/ADV7311 can be used to lock
F
7
This reset signal will have to be held high for a minimum of
one clock cycle.
Since the field counter is not reset, it is recommended that
the reset signal be applied in Field 7 [PAL] or Field 3 [NTSC].
The reset of the phase will then occur on the next field, i.e.,
Field 1, being lined up correctly with the internal counters.
The field count register at Address 7Bh can be used to iden-
tify the number of the active field.
to an external video source. The real-time control mode allows
the ADV7310/ADV7311 to automatically alter the subcarrier
frequency to compensate for line length variations. When the
part is connected to a device that outputs a digital data stream
in the RTC format, such as an ADV7183A video decoder
(see Figure 32), the part will automatically change to the
compensated subcarrier frequency on a line by line basis. This
digital data stream is 67 bits wide and the subcarrier is con-
tained in Bits 0 to 21. Each bit is two clock cycles long. 00h
should be written into all four subcarrier frequency registers
when this mode is used.
SC
PHASE = FIELD 1
21
F
320
F
SC
320
320
SC
F
PHASE = FIELD 4 OR 8
SC
PHASE = FIELD 4 OR 8
PHASE = FIELD 1
TIMING RESET PULSE
F
SC
RESET PULSE
REV. A