HMP8156ACNZ Intersil, HMP8156ACNZ Datasheet - Page 6

• Manufacturer Part Number: HMP8156ACNZ
• Description: IC VIDEO ENCODER NTSC/PAL 64MQFP
• Manufacturer: Intersil
• Type: NTSC/PAL Encoderr

Specifications of HMP8156ACNZ

• Applications: Multimedia, Video Editing
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Package / Case: 64-MQFP, 64-PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NOTES:
Normal 8-Bit YCbCr Format
When 8-bit YCbCr format is selected and 2X upscaling or
flicker filtering is not enabled, the data is latched on each
rising edge of CLK2. The pixel data must be [Cb Y Cr Y’ Cb Y
Cr Y’ . . . ], with the first active data each scan line being Cb
data. Overlay data is latched when the Y input data is latched.
The pixel and overlay input timing is shown in Figure 1.
As inputs, BLANK, HSYNC, and VSYNC are latched on
each rising edge of CLK2. As outputs, BLANK, HSYNC, and
VSYNC are output following the rising edge of CLK2. If the
CLK pin is configured as an input, it is ignored. If configured
as an output, it is one-half the CLK2 frequency.
1. Encoder operating modes:
2. Video timing control signals include HSYNC, VSYNC, BLANK and FIELD. The sync and blanking I/O directions are independent; FIELD is always
INPUT FORMAT
16-Bit YCbCr,
Norm = Full size input, Flicker filter disabled.
2X = SIF size input, Flicker filter disabled.
FF = Full size input, Flicker filter enabled.
(2X upscaling and flicker filtering are mutually exclusive.)
an output.
8-Bit YCbCr
16-Bit RGB,
24-Bit RGB
BT.656
or
Norm
Norm
Norm
2X
FF
2X
FF
2X
FF
Every rising edge
of CLK2
Rising edge of
CLK2 when CLK is
low.
Rising edge of CLK2 when CLK is low
2nd rising edge of CLK2 when CLK is low
Every rising edge
of CLK2
Every rising edge
of CLK2
6
PIXEL DATA
INPUT PORT SAMPLING
TABLE 5. PIXEL INPUT AND CONTROL SIGNAL I/O TIMING
Same edge that
latches Y
Same edge that
latches Y data
Same edge that
latches Y
Same edge that
latches Y
OVERLAY DATA
HMP8154, HMP8156A
Every rising edge
of CLK2
Rising edge of
CLK2 when CLK is
low.
Every rising edge
of CLK2
Not Allowed
VIDEO TIMING CONTROL (NOTE 2)
INPUT SAMPLE
8-Bit YCbCr Format with 2X Upscaling
When 8-bit YCbCr format is selected and 2X upscaling is
enabled, the data is latched on the rising edge of CLK2 while
CLK is low. The pixel data must be [Cb Y Cr Y’ Cb Y Cr
Y’. . . ], with the first active data each scan line being Cb
data. Overlay data is latched on the rising edge of CLK2 that
latches Y pixel input data. The pixel and overlay input timing
is shown in Figure 2.
As inputs, BLANK, HSYNC, and VSYNC are latched on the
rising edge of CLK2 while CLK is low. As outputs, HSYNC,
VSYNC, and BLANK are output following the rising edge of
CLK2 while CLK is high. In this mode of operation, CLK is
one-half the CLK2 frequency.
Not Available
Not Available
Not Available
Any rising edge of
CLK2
Rising edge of
CLK2 when CLK is
high.
Rising edge of
CLK2 when CLK is
high.
Either rising CLK2
edge when CLK is
high
Any rising edge of
CLK2
Any rising edge of
CLK2
OUTPUT ON
Ignored
Ignored
Ignored
INPUT
CLK FREQUENCY
One-fourth CLK2
One-half CLK2
One-half CLK2
One-half
CLK2
One-half
CLK2
One-half
CLK2
August 20, 2009
OUTPUT
FN4343.5