ADV7303AKST Analog Devices Inc, ADV7303AKST Datasheet - Page 16

IC DAC VIDEO HDTV 6-11BIT 64LQFP

ADV7303AKST

Manufacturer Part Number
ADV7303AKST
Description
IC DAC VIDEO HDTV 6-11BIT 64LQFP
Manufacturer
Analog Devices Inc
Type
Video Encoderr
Datasheet

Specifications of ADV7303AKST

Rohs Status
RoHS non-compliant
Applications
DVD, Set-Top Boxes
Voltage - Supply, Analog
2.37 V ~ 2.63 V
Voltage - Supply, Digital
2.37 V ~ 3.6 V
Mounting Type
Surface Mount
Package / Case
64-LQFP
Number Of Dac's
6
Adc/dac Resolution
11b
Screening Level
Commercial
Package Type
LQFP
Pin Count
64
Lead Free Status / RoHS Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ADV7303AKST
Manufacturer:
AD
Quantity:
1
ADV7302A/ADV7303A
NOTES
1
2
When enabled, the current consumption is reduced to µA level. All DACs and the internal PLL cct are disabled. I
This control allows the internal PLL circuit to be powered down and the oversampling to be switched off.
Subaddress
00h
Subaddress Register
01h
Register
Power Mode Register
Input Mode Register
Bit Description
Sleep Mode
PLL and Oversampling
Control
DAC F: Power On/Off
DAC E: Power On/Off
DAC D: Power On/Off
DAC C: Power On/Off
DAC B: Power On/Off
DAC A: Power On/Off
Bit Description
BTA T-1004 Compatibility
Reserved
Pixel Align
Clock Align
Input Mode
Reserved
2
1
Table I. Power Mode Register
Table II. Input Mode Register
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting
0
1
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting
0
–16–
0
1
0
0
0
0
1
1
1
1
0
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2
C registers can be read from and written to.
0
1
0
0
1
0
1
Sleep Mode Off
Sleep Mode On
PLL On
PLL Off
DAC F Off
DAC F On
DAC E Off
DAC E On
DAC D Off
DAC D On
DAC C Off
DAC C On
DAC B Off
DAC B On
DAC A Off
DAC A On
Disabled
Enabled
Zero must be written
to this bit.
Video input data starts
with a Y0 bit. Only for
PS Interleaved Mode.
Video input data starts
with a Cb0 bit.
Must be set if the
phase delay between
the two input clocks is
<9.25 ns or >27.75 ns.
Only if two input
clocks are used.
SD Input Only
PS Input Only
HDTV Input Only
SD and PS (16-Bit)
SD and PS (8-Bit)
SD and HDTV (SD
Oversampled)
SD and HDTV
(HDTV Oversampled)
PS 54 MHz Input
Zero must be written
to this bit.
Reset
Fch
Reset
38h
REV. A

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