SAA7134HL/V1,557 NXP Semiconductors, SAA7134HL/V1,557 Datasheet - Page 9

• Manufacturer Part Number: SAA7134HL/V1,557
• Description: IC AUD/VID DECODER PCI 128LQFP
• Manufacturer: NXP Semiconductors
• Type: Video Decoderr

Specifications of SAA7134HL/V1,557

• Package / Case: 128-LQFP
• Applications: TV
• Voltage - Supply, Analog: 3 V ~ 3.6 V
• Voltage - Supply, Digital: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935269247557; SAA7134HLBE; SAA7134HLBE

Philips Semiconductors
SAA7134HL_4
Product data sheet
Table 5:
[1]
Table 6:
Symbol
PCI_CLK
PCI_RST#
AD[31] to AD[00] 4 to 11,
C/BE[3]# to
C/BE[0]#
PAR
FRAME#
TRDY#
IRDY#
STOP#
IDSEL
DEVSEL#
REQ#
GNT#
INT_A
PERR#
SERR#
Symbol
XTALI
XTALO
LEFT2
PCI-bus pins are located on the long side of the package to simplify PCI board layout requirements.
PCI interface pins
Analog interface pins
Pin
40
127
14 to 18,
21 to 23,
34 to 37,
41 to 44
and
46 to 53
12, 24,
33
and 45
32
25
27
26
29
13
28
3
2
126
30
31
Pin
62
63
94
Rev. 04 — 31 March 2006
Type
PI
PI
PIO and
T/S
PIO and
T/S
PIO and
T/S
PIO and
S/T/S
PIO and
S/T/S
PIO and
S/T/S
PIO and
S/T/S
PI
PIO and
S/T/S
PO
PI
PO and
O/D
PIO and
S/T/S
PO and
O/D
Type
CI
CO
AI
[1]
[1]
Description
PCI clock input: reference for all bus transactions, up to
33.33 MHz
PCI reset input: will 3-state all PCI pins (active LOW)
multiplexed address and data input or output:
bi-directional, 3-state
command code input or output: indicates type of
requested transaction and byte enable, for byte aligned
transactions (active LOW)
parity input or output: driven by the data source, even
parity over all pins AD and C/BE#
frame input or output: driven by the current bus master
(owner), to indicate the beginning and duration of a bus
transaction (active LOW)
target ready input or output: driven by the addressed
target, to indicate readiness for requested transaction
(active LOW)
initiator ready input or output: driven by the initiator, to
indicate readiness to continue transaction (active LOW)
stop input or output: target is requesting the master to
stop the current transaction (active LOW)
initialization device select input: this input is used to select
the SAA7134HL during configuration read and write
transactions
device select input or output: driven by the target device,
to acknowledge address decoding (active LOW)
PCI request output: the SAA7134HL requests master
access to PCI-bus (active LOW)
PCI grant input: the SAA7134HL is granted to master
access PCI-bus (active LOW)
interrupt A output: this pin is an open-drain interrupt
output, conditions assigned by the interrupt register
parity error input or output: the receiving device detects
data parity error (active LOW)
system error output: reports address parity error (active
LOW)
Description
quartz oscillator input: 32.11 MHz or 24.576 MHz
quartz oscillator output
analog audio stereo left 2 input or mono input
PCI audio and video broadcast decoder
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
SAA7134HL
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