LTC1164CSW Linear Technology, LTC1164CSW Datasheet - Page 7

• Manufacturer Part Number: LTC1164CSW
• Description: IC FILTER BUILDING BLOCK 24-SOIC
• Manufacturer: Linear Technology

Specifications of LTC1164CSW

• Filter Type: Universal Switched Capacitor
• Frequency - Cutoff Or Center: 20kHz
• Number Of Filters: 4
• Max-order: 8th
• Voltage - Supply: ±2.37 V ~ 8 V
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: LTC1164CS

PI FU CTIO S
Power Supplies (Pins 7,19)
They should be bypassed with 0.1µF ceramic disc. Low
noise, non-switching, power supplies are recommended.
The device operates with a single 5V supply and with dual
supplies. The absolute maximum operating power supply
voltage is ±8.25V. Supply reversal is not allowed and can
cause latch up. When using dual supplies, loads between
the positive and negative supply (even light loads) can
cause momentary supply reversal during power-up. A
clamp diode from each supply to ground will prevent
reversal and latch problems.
Clock (Pin 18)
For ±5V supplies the logic threshold level is 1.8V. For ±8V
and 0 to 5V supplies the logic threshold level is 2.8V. The
logic threshold levels vary ±100mV over the full military
temperature range. The recommended duty cycle of the
input clock is 50%, although for clock frequencies below
500kHz the clock “on” time can be as low as 200ns. The
maximum clock frequency for single 5V supply and Q
values <5 is 500kHz and for ±5V supplies and above is
1MHz. The clock input can be applied before power is
turned on as long as there is no chance the clock signal will
go below the V
U
U
–
supply.
*LT1004 CAN BE REPLACED WITH A 7.5k RESISTOR FOR V
NOTE: PIN 5, 8, 20, IF NOT USED, SHOULD BE CONNECTED TO PIN 6.
U
0.1µF
+
4.7µF
GROUND
ANALOG
PLANE
V
+
7.5k
LT1004*
Figure 2. Single Supply Operation
V
+
/2
0.1µF
+
>6.5V
10
11
12
1
2
3
4
5
6
7
8
9
AGND
V
+
AGND (PIN 6)
When the LTC1164 operates with dual supplies, Pin 6
should be tied to system ground. When the LTC1164
operates with a single positive supply, the analog ground
pin should be tied to 1/2 supply and it should be bypassed
with a 4.7µF solid tantalum in parallel with a 0.1µF ceramic
disc, Figure 2. The positive input of all the internal op
amps, as well as the common reference of all the internal
switches, are internally tied to the analog ground pin.
Because of this, a very “clean” ground is recommended.
50/100 (Pin 17)
By tying Pin 17 to V
to-center frequency ratio internally set at 50:1. When Pin
17 is at mid-supplies, sections B and C operate with (f
f
Pin 17 is shorted to the negative supply pin, all filter
sections operate with (f
O
LTC1164
) = 50:1 and sections A and D operate at (100:1). When
50/100
CLK
V
–
24
23
22
21
20
19
18
17
16
15
14
13
LTC1164 • PD01
+
, all filter sections operate with a clock-
CLK
/f
TO DIGITAL
GROUND
O
CLOCK INPUT
V
V
V
) = 100:1.
+
+
+
= 15V, TRIP VOLTAGE = 7V
= 10V, TRIP VOLTAGE = 6.4V
= 5V, TRIP VOLTAGE = 3V
LTC1164
CLK
1164fa
7
/