XW2B-80J7-1A Omron, XW2B-80J7-1A Datasheet - Page 178

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XW2B-80J7-1A

Manufacturer Part Number
XW2B-80J7-1A
Description
RELAY UNIT
Manufacturer
Omron
Datasheet

Specifications of XW2B-80J7-1A

Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
XW2B80J71A
Checking for High-speed
Counter Interrupts
Pulse Inputs
Note
■ Phase-Z Signal (Reset Input) and Software Reset
■ Software Reset
■ Target-value Comparison Method
The PV of the high-speed counter is reset on the first rising edge of the
phase-Z signal after the corresponding High-speed Counter Reset Bit (see
below) turns ON.
The PV is reset when the High-speed Counter Reset Bit turns ON. There are
separate Reset Bits for high-speed counters 1 and 2.
The High-speed Counter Reset Bits are as follows:
The High-speed Counter Reset Bits are refreshed only once each cycle, so a
Reset Bit must be ON for a minimum of 1 cycle to be read reliably.
The comparison table registration and comparison execution status will not be
changed even if the PV is reset. If a comparison was being executed before
the reset, it will continue.
The following two methods are available to check the PV of high-speed
counters 1 or 2.
Up to 48 target values and corresponding interrupt task numbers can be reg-
istered in the comparison table. When the counter PV matches one of the 48
registered target values, the specified interrupt task will be executed.
Comparisons are made to each target value in the order that they appear in
the comparison table until all values have been met, and then comparison will
return to the first value in the table.
Reset Bit for
High-speed
Counter 1 or 2
Counter 1 or 2
Reset Bit for
(reset input)
High-speed
• High-speed Counter 1 Reset Bit: A610.01
• High-speed Counter 2 Reset Bit: A611.01
• Target-value comparison method
• Range comparison method
Phase-Z
1 or more cycles
Within 1 cycle
Reset by cycle.
Reset
1 or more cycles
Within 1 cycle
Reset by cycle.
1 or more cycles
Section 7-5
Not reset.
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