SI2493-C-FS Silicon Laboratories Inc, SI2493-C-FS Datasheet - Page 101

• Manufacturer Part Number: SI2493-C-FS
• Description: IC ISOMODEM SYSTEM-SIDE 16SOIC
• Manufacturer: Silicon Laboratories Inc

Specifications of SI2493-C-FS

• Mfg Application Notes: SI2493/57/34/15/04, Appl Note AN93
• Data Format: V.21, V.22, V.23, V.29, V.32, V.34, V.90, V.92, Bell 103, Bell 212A
• Baud Rates: 56k
• Interface: UART
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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3.4.4. Parallel Interface
The parallel interface is intended for applications where
a serial interface is not available. The parallel interface
has an 8-bit data bus and a single address bit. The
parallel interface is selected by forcing AOUT/INT
(Si2493/57/34/15/04 Pin 15) to a logic 0 (low) through
an
operation is possible in parallel mode. See Table 24 on
page 57 for details. Several pins on the Si2457 change
function when the parallel interface mode is selected. In
parallel mode, the modem must be configured for a DTE
Interface or 8N1 only. The host processor must
calculate parity for MSB. The modem sends bits as
received by the host and does not calculate parity. Refer
to
Software” for detailed parallel interface applications
information*.
“AN60:
external
(24-Pin TSSOP Only)
Si2493/57/34/15/04
pulldown
resistor
TX FIFO
Register
TX Shift
TXD
(10)
Parallel
≤ 10 kΩ.
Figure 19. UART Serial Interface
CTS
Interface
(11)
27 MHz
CONTROL
RTS
(8)
Rev. 0.9
MUX
*Note: The parallel port has been modified in Si2456
Table 71 shows the function of the affected pins in the
serial and parallel interface modes.
11 Bits
to Data Bus
(16)
INT
Revision H and Si2457 Revision B and later to allow
interrupt-driven operation and remove the requirement
of using CTS and RTS for flow control (see “AN60:
Si2456/33/14 Parallel Interface Software”). Updates
that may affect existing host software written for the
Si2456 family with revisions before Revision H or the
Si2457 family Revision A are:
1. It is possible to clear the RXF bit by writing “0” in this
bit position of parallel register 1. It is recommended
that this bit always be written with “1” unless
intentionally clearing the RXF bit to remove an RXF
interrupt.
2. An inactivity timer controlled by register U6F will
assert an interrupt if data is available in the RX FIFO
for U6F milliseconds (default 255). This is important to
note when upgrading a hardware design from the
Si2456 family to the Si2457 family. A small change to
existing host software may be necessary.
RX Shift
Register
RX FIFO
RXD
(9)
AN93
101